CS493253-CLZ Cirrus Logic Inc, CS493253-CLZ Datasheet - Page 89

• Manufacturer Part Number: CS493253-CLZ
• Description: Audio DSPs IC Multi-Standard Audio Decoder
• Manufacturer: Cirrus Logic Inc

Specifications of CS493253-CLZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15. DOCUMENT REVISIONS
DS339F7
PP4
F1
F2
F3
F4
F5
F6
F7
Revision
Mar 2003
Feb 2004
Apr 2004
APR 2005
JUN 2005
NOV 2005
JAN 2006
APR 2006
Date
Last preliminary release.
Initial final release.
1. p.73, Corrected Hex Message ”B” Value 74 from:
2. p. 84, Added ROM ID-5 devices and a note on ordering lead-free devices to
“Ordering Information”. Also added a description of the characters that comprise
the part number.
3. Removed ambient temperature condition (T
4. Changed Note 6. in Table 1.9 (p.12) and Table 1.10 (p.14) from:
With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open
drain adjusting the pull up value will affect the rise time.
to
With a 3.3k Ohm pull-up resistor this value is typically 260ns. As this pin is open
drain adjusting the pull up value will affect the rise time.
5. Added a section “2.1. - CS493XX Document Strategy” (p.21)
6. p.10, Changed CS to DS for T
7. p.10, Deleted the word “low” from the Parameter column for T
8. p. 84 Added two diagrams that indicate how to determine the “Device Revi-
sion Level” from the 10-character or the 12-character Pack Mark written on the
top of chip, below the device number.
9. p. 80, Made reference to the use of pin 4 & pin 5 as mode select pin at reset.
Also added that both these pins require 3.3 k Ohm pull-up or pull-down
10. p. 81, Changed pin 19 & pin 20 pull-up/down resistor requirement to 3.3 k
Ohm. Also mention of pin 19 usage as a mode select pin during reset.
Changed “All bidirectional pins high-Z after RESET low” ( T
50ns Max to 100ns Max. See page 8.
Updated Device Ordering Information to include Pb-free devices.
Corrected error in mechanical information - “e”, pin spacing from .102 mm to
1.016 mm
Updated CLKIN high/low times to 14 ns. Added “Delay from falling edge of
CMPREQ to CMPCLK rising edge” parameter to Serial Bursty Data Input timing
(0 ns). Updated same timing diagram to include T
AddedThermal Data section (section 1.3)
Added Note 3 and Note 4 to
copyright date.
0x0014C0 to 0x0028C0
Section 1.3, “Thermal Data” on page
mdd
Changes
CS49300 Family DSP
A
=25
reqclk
°
C) from Spec Tables.
parameter.
rst2z
) parameter from
mdis
7. Corrected
89