UDA1380TT NXP Semiconductors, UDA1380TT Datasheet - Page 19

• Manufacturer Part Number: UDA1380TT
• Description: Audio CODECs SSA CODEC
• Manufacturer: NXP Semiconductors

Specifications of UDA1380TT

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-32
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: UDA1380TT/N2,512

Philips Semiconductors
8.11.1
Figure 12 shows the power control inside the analog front-end. The control of all power-on pins of the ADC front-end is
done via separate L3-bus or I
8.11.2
The FSDAC block has power-on pins: one of which shuts
down the DAC itself, but leaves the output still at V
voltage (which is half the power supply). This function is
set by the bit PON_DAC in the L3-bus or I
A second L3-bus or I
bias circuit of the FSDAC, via bit PON_BIAS in the
L3-bus or I
same as given in Fig.12 for the analog front-end.
8.12
Plops are ticks and other strange sounds that can occur
when a part of a device is powered-up or powered-down,
or when switching between modes is done.
Some ways to prevent plops from occurring are:
2004 Apr 22
handbook, full pagewidth
When the FSDAC or headphone driver must be
powered-down, first a digital mute is applied. After that
Stereo audio coder-decoder
for MD, CD and MP3
Pin numbers for UDA1380HN in parentheses.
Plop prevention
A
FSDAC
NALOG FRONT
2
C-bus register. This bit PON_BIAS acts the
POWER CONTROL
2
VINM
VINR
C-bus bit shuts down the complete
VINL
-
END
PGA_GAINCTRLL
(29)
(27)
(31)
1
31
3
2
C-bus bits.
PGA_GAINCTRLR
PON_LNA
PGA
PGA
LNA
PON_PGAL
Fig.12 Analog front-end power-down.
2
C-bus register.
PON_PGAR
SDC
SDC
SDC
REF
PON_ADCL
19
ADC
ADC
Remark: All items mentioned in Section 8.12 are not
‘hard-wired’ implemented, but are to be followed by the
user as a guideline for plop prevention.
PON_ADCR
the FSDAC or headphone driver can be powered-down.
In case the FSDAC or headphone driver must be
powered-up, first the analog part is switched on, then the
digital part is demuted
When the ADC must be powered-down, a digital mute
sequence must be applied. When the digital output
signal is completely muted, the ADC can be
powered-down. In case the ADC must be powered-up,
first the analog part must be powered-up, then the digital
part must be demuted
When there is a change of, for example, clock divider
settings or clock source (selecting between SYSCLK
and WSPLL clock), then also digital mute for that block
(either decimator or interpolator) should be used.
BIAS
FE
MGU534
PON_BIAS
V REF
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Product specification
UDA1380