CY2SSTV857ZXC-32 Silicon Laboratories Inc, CY2SSTV857ZXC-32 Datasheet
CY2SSTV857ZXC-32
Specifications of CY2SSTV857ZXC-32
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CY2SSTV857ZXC-32 Summary of contents
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Differential Clock Buffer/Driver DDR400/PC3200-Compliant Features • Operating frequency: 60 MHz to 230 MHz • Supports 400 MHz DDR SDRAM • 10 differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < ...
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VDDQ CLK# VDDQ AVDD AVSS Pin Description Pin # Pin # 48 TSSOP 40 QFN 13, 14 5,6 CLK, CLK 10, 20, 22 37,39,3,12, 19, 23 36,40,2,11,15 27, 29, 39, 44, ...
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Zero Delay Buffer When used as a zero delay buffer the CY2SSTV857-32 will likely nested clock tree application. For these applica- tions, the CY2SSTV857-32 offers a differential clock input pair as a PLL reference. The CY2SSTV857-32 then ...
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CLKIN Yx or FBIN Yx DDR _SDRAM represents a capacitive load CLK 120 Ohm CLK# 120 Ohm Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< Rev 1.0, November 21, 2006 t pd Figure 2. Propagation Delay ...
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DDR-SDRAM represents a capacitive load CLK 120 Ohm CLK# 120 Ohm Output load capacitancce for 4 DDR-SDRAM Loads < CL < ...
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Absolute Maximum Conditions Input Voltage Relative to V :............................... V SS Input Voltage Relative DDQ DD Storage Temperature: ................................ –65° 150°C Operating Temperature:................................ –40°C to +85°C Maximum Power Supply: ................................................ 3.5V [3] DC Electrical ...
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... TSSOP–Tape and Reel [15] CY2SSTV857LFI–32 40-pin QFN [15] CY2SSTV857LFI–32T 40-pin QFN–Tape and Reel Lead-Free CY2SSTV857ZXC–32 48-pin TSSOP CY2SSTV857ZXC–32T 48-pin TSSOP–Tape and Reel [15] CY2SSTV857LFXC–32 40-pin QFN [15] CY2SSTV857LFXC–32T 40-pin QFN–Tape and Reel CY2SSTV857ZXI–32 48-pin TSSOP CY2SSTV857ZXI– ...
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Package Drawing and Dimension 0.500[0.019 12.395[0.488] 12.598[0.496] 0.500[0.020] 0.851[0.033] BSC 0.950[0.037] DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-220 TOP VIEW 5.90[0.232] A 6.10[0.240] 5.70[0.224] 5.80[0.228 0.60[0.024] DIA. While SLI has reviewed all information herein ...