CY2SSTV857ZXC-32 Silicon Laboratories Inc, CY2SSTV857ZXC-32 Datasheet - Page 3

• Manufacturer Part Number: CY2SSTV857ZXC-32
• Description: Clock Buffer 2.5V 60-200MHz 1:10 Diff DDR266/333 B/D
• Manufacturer: Silicon Laboratories Inc

Specifications of CY2SSTV857ZXC-32

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV857-32 will
likely be in a nested clock tree application. For these applica-
tions, the CY2SSTV857-32 offers a differential clock input pair
as a PLL reference. The CY2SSTV857-32 then can lock onto
the reference and translate with near zero delay to low-skew
outputs. For normal operation, the external feedback input,
FBIN, is connected to the feedback output, FBOUT. By
connecting the feedback output to the feedback input the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs.
Table 1. Function Table
AVDD
GND
GND
2.6V
2.6V
2.6V
X
X
PD#
H
H
H
H
H
L
L
Inputs
< 20 MHz
CLKIN
FBOUT
CLK
H
H
H
FBIN
L
L
L
Yx
Yx
Yx
< 20 MHz
Figure 1. Phase Error and Skew Waveforms
CLK#
H
H
H
L
L
L
t
t
(phase error)
t
sk(o)
sk(o)
Hi-Z
Y
H
Z
Z
H
L
L
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Power Management
Output enable/disable control of the CY2SSTV857-32 allows
the user to implement power management schemes into the
design. Outputs are three-stated/disabled when PD# is
asserted LOW (see Table 1).
Hi-Z
Y#
H
Z
Z
H
L
L
Outputs
FBOUT
Hi-Z
H
H
L
Z
Z
L
FBOUT#
HI-Z
H
Z
Z
H
L
L
CY2SSTV857-32
BYPASSED/OFF
BYPASSED/OFF
Page 3 of 8
OFF
PLL
Off
On
On
Off