SL28748ELC Silicon Laboratories Inc, SL28748ELC Datasheet - Page 8

• Manufacturer Part Number: SL28748ELC
• Description: Clock Generators & Support Products Calpella IronLake Jasper Forest IbexPk
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28748ELC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DOC#: SP-AP-0017 (Rev. AA)
Byte 10: Control Register 10 (continued)
Byte 11: Control Register 11
Byte 12: Byte Count
Byte 13: Control Register 13
Bit
Bit
Bit
Bit
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
@Pup
@Pup
@Pup
@Pup
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
CPU1_STP_CTRL
CPU0_STP_CTRL
27MHz_NSS_Bit2
27MHz_NSS_Bit0
CPU1_iAMT_EN
27MHz_SS_Bit2
27MHz_SS_Bit0
PCI-e_GEN2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
REF_Bit2
REF_Bit0
Name
Name
Name
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
CPU1 iAMT Clock Enabled
RESERVED
RESERVED
RESERVED
Enable CPU_STP# control of CPU1
0 = Free running, 1= Stoppable
Enable CPU_STP# control of CPU0
0 = Free running, 1= Stoppable
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0 = Disabled, 1 = Enabled
PCI-e_Gen2 Compliant
0 = non Gen2, 1= Gen2 Compliant
RESERVED
Byte count register for block read operation.
The default value for Byte count is 15.
In order to read beyond Byte 15, the user should change the byte count
limit.to or beyond the byte that is desired to be read.
Drive Strength Control - Bit[2:0],
Byte 6 Bit 3 for 27MHz Slew Rate Bit 1
Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
Description
Description
Description
Description
Note: See Byte 6 Bit 5 for REF Slew Rate Bit 1 and
SL28748
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