SL28610BLCT Silicon Laboratories Inc, SL28610BLCT Datasheet - Page 11

• Manufacturer Part Number: SL28610BLCT
• Description: Clock Generators & Support Products AtomPoulsbo Handheld Embed.1.5V PCIe G1
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28610BLCT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Byte 20: Control Register 20
Byte 21: Control Register 21
CKPWRGD#/PD (Power down) Clarification
The CKPWRGD#/PD pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD#. Once
CKPWRGD# has been sampled HIGH by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD is also an asynchronous input for powering up
the system. When PD is asserted HIGH, clocks are driven to
a LOW value and held before turning off the VCOs and the
crystal oscillator.
CKPWRGD#/PD (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held HIGH on their
...................... DOC #: SP-AP-0078 (Rev. AA) Page 11 of 23
Bit
Bit
7
6
5
4
7
2
1
0
7
6
5
4
7
2
1
0
@Pup
@Pup
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PLL3_DAF_N7
PLL3_DAF_N6
PLL3_DAF_N5
PLL3_DAF_N4
PLL3_DAF_N3
PLL3_DAF_N2
PLL3_DAF_N1
PLL3_DAF_N0
PLL3_DAF_M7
PLL3_DAF_M6
PLL3_DAF_M5
PLL3_DAF_M4
PLL3_DAF_M3
PLL3_DAF_M2
PLL3_DAF_M1
PLL3_DAF_M0
Name
Name
If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and
PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.
If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and
PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.
next HIGH-to-LOW transition and differential clocks must held
HIGH. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
CKPWRGD#/PD (Power Down) Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
Description
Description
SL28610