DS26503L Maxim Integrated Products, DS26503L Datasheet - Page 48

• Manufacturer Part Number: DS26503L
• Description: Timers & Support Products E1-T1-J1 BITS Elemen t T1-E1-J1 BITS Elem
• Manufacturer: Maxim Integrated Products
• Type: Clock Recoveryr

Specifications of DS26503L

• Supply Voltage (max): 3.46 V
• Supply Voltage (min): 3.13 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Current: 85 mA
• Package / Case: LQFP-64

9.2 E1 Information Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in
error.
Bit 1: FAS Resync Criteria Met Event (FASRC. Set when three consecutive FAS words are received in error.
Bit 2: CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error.
Bits 3 to 7: Unused
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment word.
Bit 1: CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.
Bit 2: FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level.
Bits 3 to 7: CRC4 Sync Counter Bits (CSC0 and CSC2 to CSC5). The CRC4 sync counter increments each time the 8ms-
CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the
CRC4 level. The counter can also be cleared by disabling CRC4 mode. This counter is useful for determining the amount of
time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the
CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. The CRC4 sync
counter will rollover. CSC0 is the LSB of the 6-bit counter. (Note: The second LSB, CSC1, is not accessible. CSC1 is omitted
to allow resolution to >400ms using 5 bits.)
CSC5
—
X
X
7
0
7
0
CSC4
—
INFO2
Information Register 2
12h
INFO3
Information Register 3 (Real Time)
1Ch
X
X
6
0
6
0
CSC3
—
X
X
5
0
5
0
CSC2
—
X
X
4
0
4
0
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CSC0
—
X
X
3
0
3
0
CRCRC
FASSA
X
X
2
0
2
0
FASRC
CASSA
X
X
DS26503 T1/E1/J1 BITS Element
1
0
1
0
CRC4SA
CASRC
X
X
0
0
0
0