MAX3878EHJ Maxim Integrated Products, MAX3878EHJ Datasheet - Page 10

• Manufacturer Part Number: MAX3878EHJ
• Description: Timers & Support Products 2.5Gbps, +3.3V Clock and Data Retiming I
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Retimingr

Specifications of MAX3878EHJ

• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 163 mA
• Package / Case: TQFP-32 EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The internal clock is aligned to the center of the data
eye. For specific applications, this sampling position
can be shifted using the PHADJ input to optimize BER
performance. Refer to Figure 6 for setting the voltage at
PHADJ. When the phase adjust feature is not used,
PHADJ should be tied directly to V
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, C
is required to set the PLL damping ratio. Refer to
Design Procedure for guidelines on selecting this
capacitor.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low phase noise
and is trimmed to the correct frequency. Clock jitter
generation is typically 1.2ps
width of 12kHz to 20MHz.
A loss-of-lock monitor is incorporated in the
MAX3877/MAX3878 frequency detector. When the PLL
is frequency locked, the internal LOL signal is high, and
if the PLL is out of frequency lock, the internal LOL sig-
nal immediately becomes low.
A loss of signal detector is provided to detect a loss of
incoming data. If there are no transitions to the SDI
data input for approximately 1.65µs, the LOS signal
becomes high.
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
Figure 6. Phase Alignment vs. PHADJ Voltage
10
______________________________________________________________________________________
-100
100
-50
50
0
0.2
PHASE ALIGNMENT vs. PHADJ VOLTAGE
0.7
PHADJ VOLTAGE
Loss-of-Signal Detector
Loss-of-Lock Monitor
1.2
Loop Filter and VCO
RMS
CC
within a jitter band-
1.7
.
Phase Adjust
2.2
F
,
The input signal is first limited in the forward signal path.
The DC offset of this signal is detected and then amplified
in the feedback path. C
the low pass filter. This error signal is then subtracted
from the incoming data. When threshold adjust is
enabled, this loop acts as a pulse-width distortion cancel-
lation loop. Shorting the C
the DC-offset/pulse-width distortion cancellation loop.
This analog input controls the decision threshold of the
input stage. In applications where the noise density is not
balanced between logical zeros and ones (i.e., optical
amplification using EDFA amplifiers), it is possible to
achieve lower bit-error ratios (BER) by adjusting the input
threshold. Threshold adjust may be disabled by connect-
ing THADJ to V
the center of the differential input voltage swing at the
input. Refer to Figures 3 and 7 for setting the voltage at
THADJ.
TTL inputs SIS and LREF are provided to select between
the SDI and SLBI inputs. Table 1 is a logical truth table
describing the operation of SIS and LREF. In this way,
the MAX3877/MAX3878 will automatically lock to the ref-
erence clock in the event of a loss-of-signal condition.
In systems where a valid clock output is required under
loss-of-signal conditions, a 155MHz reference clock is
applied to the SLBI inputs for holdover capabilities. This
holdover mode is activated with the LREF input. LREF
may be directly connected to the LOS pin or to an exter-
nal system loss-of-signal monitor.
Figure 7. Threshold Level vs. THADJ Voltage
-180
180
-90
90
0
DC-Offset/Pulse-Width Distortion
0.2
CC
THRESHOLD LEVEL vs. V
. The threshold level is set relative to
0.7
PWD
THADJ VOLTAGE
PWD
sets the cutoff frequency of
1.2
± pins together disables
Cancellation Loop
Input Select Pins
Threshold Adjust
TH
1.7
VOLTAGE
2.2