MAX3878EHJ Maxim Integrated Products, MAX3878EHJ Datasheet - Page 8

• Manufacturer Part Number: MAX3878EHJ
• Description: Timers & Support Products 2.5Gbps, +3.3V Clock and Data Retiming I
• Manufacturer: Maxim Integrated Products
• Type: Clock and Data Retimingr

Specifications of MAX3878EHJ

• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 163 mA
• Package / Case: TQFP-32 EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
8
3, 6, 11, 14,
1, 9, 10,16,
15, 17, 20,
_______________________________________________________________________________________
21, 24
PIN
30
12
13
18
19
22
23
25
26
27
28
29
31
32
2
4
5
7
8
SCLKO+
SCLKO-
CPWD+
PHADJ
CPWD-
THADJ
NAME
SLBI+
SDO+
SLBI-
SDO-
LREF
GND
SDI+
FIL+
SDI-
LOL
LOS
V
FIL-
SIS
CC
Supply Ground
Supply Voltage
Threshold Control Voltage Input. Used for setting the data decision threshold. Connect to V
used. See Figure 7.
Negative Data Input. 2.488Gbps serial data stream.
Positive Data Input. 2.488Gbps serial data stream.
Signal Input Selection, TTL. High for system loopback input. See Table 1.
Lock to Reference Clock Control Signal, TTL.
Negative System Loopback or Reference Clock (in holdover mode) Input
Positive System Loopback or Reference Clock (in holdover mode) Input
Negative Clock Output, CML (MAX3877) or PECL (MAX3878)
Positive Clock Output, CML (MAX3877) or PECL (MAX3878)
Negative Data Output, CML (MAX3877) or PECL (MAX3878)
Positive Data Output, CML (MAX3877) or PECL (MAX3878)
Loss-of-Lock Indicator, TTL Active-Low
Loss-of-Signal Indicator, TTL Active-High. LOS is asserted high if there are no incoming data
transitions for approximately 1.65µs.
Phase-Adjust Input. Used to optimize sampling point. Connect to V
Negative PLL Loop Filter Connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Positive PLL Loop Filter Connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Pulse-Width Distortion Cancellation Capacitor. Connect a 0.1µF capacitor between
CPWD+ and CPWD-.
Positive Pulse-Width Distortion Cancellation Capacitor. Connect a 0.1µF capacitor between
CPWD+ and CPWD-.
FUNCTION
CC
if not used. See Figure 6.
Pin Description
CC
if not