PCK111BD NXP Semiconductors, PCK111BD Datasheet - Page 2

• Manufacturer Part Number: PCK111BD
• Description: Clock Drivers & Distribution LOWVOLT 1:10 DIFF PECL CLK DR
• Manufacturer: NXP Semiconductors
• Type: ECL, HSTL, PECLr

Specifications of PCK111BD

• Max Output Freq: 1500 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Multiply / Divide Factor: 2:1
• Number Of Clock Inputs: 2
• Output Logic Level: ECL, PECL
• Supply Voltage (max): +/- 3.8 V
• Supply Voltage (min): +/- 2.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: SOT-358
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PCK111BD,157

pairs will be used, and therefore terminated. In the case where fewer
Philips Semiconductors
FEATURES
DESCRIPTION
The PCK111 is a low skew 1-to-10 differential driver, designed with
clock distribution in mind. It accepts two clock sources into an input
multiplexer. The PECL input signals can be either differential or
single-ended if the V
out to 10 identical differential outputs.
The PCK111 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and empirical modeling
is used to determine process control limits that ensure consistent
t
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary that
both sides of the differential output are terminated into 50 , even if
only one side is being used. In most applications, all ten differential
than ten pairs are used, it is necessary to terminate at least the
output pairs on the same package side as the pair(s) being used on
that side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order of
10–20 ps) of the output(s) being used, which, while not being
catastrophic to most designs, will mean a loss of skew margin.
The PCK111 can be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Designers can take advantage of the
PCK111’s performance to distribute low skew clocks across the
backplane or the board. In a PECL environment, series or Thevenin
line terminations are typically used as they require no additional
power supplies.
The PCK111 may be driven single-endedly utilizing the V
output with the CLK0 input. If a single-ended signal is to be used,
the V
ground via a 0.01 F capacitor. The V
0.2 mA, therefore, it should be used as a switching reference for the
PCK111 only. Part-to-part skew specifications are not guaranteed
when driving the PCK111 single-endedly.
ORDERING INFORMATION
PD
Type n mber
Type number
PCK111BD
PCK111BS
2004 Apr 23
85 ps part-to-part skew typical
20 ps output-to-output skew typical
Differential design
V
Low voltage V
Low voltage V
75 k input pull-down resistors
ECL/PECL outputs
Form, fit, and function compatible with MC100EP111
Low voltage 1:10 differential
ECL/PECL/HSTL clock driver
BB
distributions from lot to lot. The net result is a dependable,
BB
output
pin should be connected to the CLK0 input and bypassed to
EE
CC
Package
Name
LQFP32
HVQFN32
range of –2.25 V to –3.8 V for ECL
range of +2.375 V to +3.8 V for PECL
BB
output is used. The selected signal is fanned
Description
plastic low profile quad flat package; 32 leads; body 7
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
BB
output can only source/sink
5
BB
0.85 mm
bias
2
PINNING
Pin configurations
CLK_SEL
CLK0
CLK0
CLK1
CLK1
CLK_SEL
V
V
V
CC
BB
EE
CLK0
CLK0
CLK1
CLK1
V
V
V
CC
7
1
2
3
4
5
6
7
8
BB
EE
Figure 2. HVQFN32 pin configuration
Figure 1. LQFP32 pin configuration
1.4 mm
1
2
3
4
5
6
7
8
PCK111BD
PCK111BS
(TOP VIEW)
Version
SOT358-1
SOT617-1
Temperature
range
–40 C to +85 C
–40 C to +85 C
PCK111
24
23
22
21
20
19
18
17
p
24
23
22
21
20
19
18
17
Product data
SW02236
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
SW00907
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6