LX128V-5F208C Lattice, LX128V-5F208C Datasheet - Page 64

• Manufacturer Part Number: LX128V-5F208C
• Description: Analog & Digital Crosspoint ICs 3.3V 128 I/O
• Manufacturer: Lattice

Specifications of LX128V-5F208C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2-256 Logic Signal Connections (Continued)
BK1_IO5
BK1_IO6
BK1_IO7
BK1_IO8
BK1_IO9
BK1_IO10/
VREF1
BK1_IO11
GND
BK1_IO12
BK1_IO13
BK1_IO14
BK1_IO15
BK1_IO17
BK1_IO18
BK1_IO19
GND
BK1_IO20
BK1_IO21
BK1_IO22
BK1_IO23
BK1_IO24
BK1_IO25
BK1_IO26
BK1_IO27
GND
BK1_IO28
BK1_IO29
BK1_IO30
BK1_IO31/
CLK_OUT2
BK2_IO1
BK2_IO2
BK2_IO3
BK2_IO5
BK2_IO6
BK2_IO7
BK2_IO8
BK2_IO9
BK1_IO16
GCLK/CE2
SEL2
SEL3
GCLK/CE3
BK2_IO0/
CLK_OUT3
GND
BK2_IO4
Signal
Name
sysIO
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
-
-
-
-
Pair/Polarity
CLK2P
CLK2N
LVDS
18N
19P
19N
20P
20N
21P
21N
22P
22N
23P
23N
24P
24N
25P
25N
26P
26N
27P
27N
28P
28N
29P
29N
30P
30N
31P
31N
32N
32P
33N
33P
34N
34P
35N
35P
36N
36P
-
-
-
-
Block MRB
GDX
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
1B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
-
-
-
-
-
-
-
-
7
7
7
7
7
7
7
7
7
7
10
11
12
13
14
15
10
11
12
13
14
15
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
-
-
-
-
-
-
-
-
HSI0B_CDRRSTb
HSI1B_CDRRSTb
FIFO0B_STRDb
FIFO1B_STRDb
SS_CLKOUT1N
SS_CLKOUT1P
SERDES Mode
HSI0B_SOUTN
HSI1B_SOUTN
HSI0_CSLOCK
HSI0B_SOUTP
HSI1B_SOUTP
HSI1_CSLOCK
HSI3_CSLOCK
HSI0B_SYDT
HSI1B_SYDT
SS_CLKIN1N
SS_CLKIN1P
HSI0B_SINN
HSI1B_SINN
HSI3A_SINN
HSI1B_SINP
HSI3A_SINP
I/O Pin
Note 4
Note 4
CAL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
61
5
5
6
6
HSI0B_RXD3/TXD3
HSI0B_RXD4/TXD4
HSI0B_RXD5/TXD5
HSI0B_RXD6/TXD6
HSI0B_RXD7/TXD7
HSI0B_RXD8/TXD8
HSI0B_RXD9/TXD9
HSI1B_RXD0/TXD0
HSI1B_RXD1/TXD1
HSI1B_RXD2/TXD2
HSI1B_RXD3/TXD3
HSI1B_RXD4/TXD4
HSI1B_RXD5/TXD5
HSI1B_RXD6/TXD6
HSI1B_RXD7/TXD7
HSI1B_RXD8/TXD8
HSI1B_RXD9/TXD9
HSI3A_RXD0/TXD0
HSI3A_RXD1/TXD1
HSI3A_RXD2/TXD2
HSI3A_RXD3/TXD3
HSI3A_RXD4/TXD4
HSI3A_RXD5/TXD5
HSI3A_RXD6/TXD6
HSI0B_RECCLK
HSI1B_RECCLK
SERDES Mode
HSI1B_SYDT
HSI3A_SYDT
I/O Cell
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
5
5
ispGDX2 Family Data Sheet
FIFO0B_DIN3/DOUT3
FIFO0B_DIN4/DOUT4
FIFO0B_DIN5/DOUT5
FIFO0B_DIN6/DOUT6
FIFO0B_DIN7/DOUT7
FIFO0B_DIN8/DOUT8
FIFO0B_DIN9/DOUT9
FIFO1B_DIN0/DOUT0
FIFO1B_DIN1/DOUT1
FIFO1B_DIN2/DOUT2
FIFO1B_DIN3/DOUT3
FIFO1B_DIN4/DOUT4
FIFO1B_DIN5/DOUT5
FIFO1B_DIN6/DOUT6
FIFO1B_DIN7/DOUT7
FIFO1B_DIN8/DOUT8
FIFO1B_DIN9/DOUT9
FIFO3A_DIN0/DOUT0
FIFO3A_DIN1/DOUT1
FIFO3A_DIN2/DOUT2
FIFO3A_DIN3/DOUT3
FIFO3A_DIN4/DOUT4
FIFO3A_DIN5/DOUT5
FIFO3A_DIN6/DOUT6
FIFO0B_FIFORSTb
FIFO1B_FIFORSTb
FIFO0B_EMPTY
FIFO1B_EMPTY
FIFO Mode I/O
FIFO1B_FULL
FIFO3A_FULL
Cell/Pin
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
fpBGA
GND
GND
GND
GND
M18
M17
P17
U18
V19
V20
V21
R16
R17
U19
U21
U22
R19
T21
N16
N17
R20
R21
N19
P20
P18
N18
R22
P22
N20
N21
K21
K20
K17
K18
H22
H21
484
T19
T20
T22
L17
L18
J17
J18
J22
J20