LX128V-5F208C Lattice, LX128V-5F208C Datasheet - Page 67

• Manufacturer Part Number: LX128V-5F208C
• Description: Analog & Digital Crosspoint ICs 3.3V 128 I/O
• Manufacturer: Lattice

Specifications of LX128V-5F208C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2-256 Logic Signal Connections (Continued)
BK4_IO21/
VREF4
BK4_IO22
BK4_IO23
BK4_IO24
BK4_IO25
BK4_IO26
BK4_IO27
BK4_IO28
BK4_IO29
BK4_IO30
BK4_IO31
GND
GOE1
TMS
GND
BK5_IO0
BK5_IO1
BK5_IO2
BK5_IO3
BK5_IO4
BK5_IO5
BK5_IO6
BK5_IO7
BK5_IO8
BK5_IO9
BK5_IO10/
VREF5
BK5_IO11
GND
BK5_IO12
BK5_IO13
BK5_IO14
BK5_IO15
BK5_IO16
BK5_IO17
BK5_IO18
BK5_IO19
GND
BK5_IO20
BK5_IO21
BK5_IO22
BK5_IO23
BK5_IO24
BK5_IO25
BK5_IO26
BK5_IO27
Signal
Name
sysIO
Bank
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
Pair/Polarity
LVDS
74P
75N
75P
76N
76P
77N
77P
78N
78P
79N
79P
80P
80N
81P
81N
82P
82N
83P
83N
84P
84N
85P
85N
86P
86N
87P
87N
88P
88N
89P
89N
90P
90N
91P
91N
92P
92N
93P
93N
-
-
Block MRB
GDX
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
-
-
-
-
-
10
11
12
13
14
15
10
11
12
13
14
15
10
11
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
-
-
-
-
-
-
HSI4B_CDRRSTb
HSI5B_CDRRSTb
FIFO4B_STRDb
FIFO5B_STRDb
SERDES Mode
HSI4B_SOUTN
HSI5B_SOUTN
HSI5A_SOUTP
HSI4_CSLOCK
HSI4B_SOUTP
HSI5B_SOUTP
HSI5_CSLOCK
HSI5A_SYDT
HSI4B_SYDT
HSI5B_SYDT
HSI5A_SINN
HSI4B_SINN
HSI5B_SINN
HSI5A_SINP
HSI4B_SINP
HSI5B_SINP
I/O Pin
Note 4
Note 4
Note 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
64
5
5
5
6
6
HSI5A_RXD9/TXD9
HSI5A_RXD8/TXD8
HSI5A_RXD7/TXD7
HSI5A_RXD6/TXD6
HSI5A_RXD5/TXD5
HSI5A_RXD4/TXD4
HSI5A_RXD3/TXD3
HSI5A_RXD2/TXD2
HSI5A_RXD1/TXD1
HSI5A_RXD0/TXD0
HSI4B_RXD9/TXD9
HSI4B_RXD8/TXD8
HSI4B_RXD7/TXD7
HSI4B_RXD6/TXD6
HSI4B_RXD5/TXD5
HSI4B_RXD3/TXD3
HSI4B_RXD2/TXD2
HSI4B_RXD1/TXD1
HSI4B_RXD0/TXD0
HSI5B_RXD9/TXD9
HSI5B_RXD8/TXD8
HSI5B_RXD7/TXD7
HSI5B_RXD6/TXD6
HSI5B_RXD5/TXD5
HSI5B_RXD4/TXD4
HSI5B_RXD3/TXD3
HSI5B_RXD2/TXD2
HSI5B_RXD1/TXD1
HSI4_RXD4/TXD4
HSI4B_RECCLK
HSI5B_RECCLK
SERDES Mode
HSI5A_SYDT
HSI4B_SYDT
I/O Cell
-
-
-
-
-
-
-
-
-
-
-
-
2
5
5
ispGDX2 Family Data Sheet
FIFO5A_DIN9/DOUT9
FIFO5A_DIN8/DOUT8
FIFO5A_DIN7/DOUT7
FIFO5A_DIN6/DOUT6
FIFO5A_DIN5/DOUT5
FIFO5A_DIN4/DOUT4
FIFO5A_DIN3/DOUT3
FIFO5A_DIN2/DOUT2
FIFO5A_DIN1/DOUT1
FIFO5A_DIN0/DOUT0
FIFO4B_DIN9/DOUT9
FIFO4B_DIN8/DOUT8
FIFO4B_DIN7/DOUT7
FIFO4B_DIN6/DOUT6
FIFO4B_DIN5/DOUT5
FIFO4B_DIN4/DOUT4
FIFO4B_DIN3/DOUT3
FIFO4B_DIN2/DOUT2
FIFO4B_DIN1/DOUT1
FIFO4B_DIN0/DOUT0
FIFO5B_DIN9/DOUT9
FIFO5B_DIN8/DOUT8
FIFO5B_DIN7/DOUT7
FIFO5B_DIN6/DOUT6
FIFO5B_DIN5/DOUT5
FIFO5B_DIN4/DOUT4
FIFO5B_DIN3/DOUT3
FIFO5B_DIN2/DOUT2
FIFO5B_DIN1/DOUT1
FIFO4B_FIFORSTb
FIFO5B_FIFORSTb
FIFO4B_EMPTY
FIFO5B_EMPTY
FIFO Mode I/O
FIFO5A_FULL
FIFO4B_FULL
Cell/Pin
-
-
-
-
-
-
-
-
-
-
3
fpBGA
GND
GND
GND
GND
484
G9
G8
G3
G2
F8
D7
D6
A6
A5
C5
B5
D5
C4
B4
A4
D2
D3
E4
D1
E1
F4
E3
H7
H6
E2
F2
G4
H5
F1
G1
K7
K6
H4
H3
H1
H2
K5
F5
J7
J6
J5