ISPGDX240VA-7BN388 Lattice, ISPGDX240VA-7BN388 Datasheet
ISPGDX240VA-7BN388
Specifications of ISPGDX240VA-7BN388
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ISPGDX240VA-7BN388 Summary of contents
Page 1
... Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.) • Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The ispGDX240VA device features fast operation, with input-to-output signal delays (Tpd) of 4.5ns and clock-to- output delays of 4.0ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Rout- ing Pool (GRP) ...
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... I/Os. ** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and CLKEN3 respectively in all devices. Specifications ispGDX240VA In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs ...
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... I/O Cell 119 240 Input GRP 120 I/O Cells Inputs Vertical Outputs Horizontal Specifications ispGDX240VA The various I/O pin sets are also shown in the block diagram below. The and D I/O pins are grouped together with one group per side. I/O Architecture ...
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... MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard and D MUX inputs, and Specifications ispGDX240VA allow adjacent I/O cell outputs to be directly connected without passing through the global routing pool. The ...
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... User-Programmable I/Os The ispGDX240VA features user-programmable Data C/ Data D/ I/Os supporting either 3.3V or 2.5V output voltage level MUXOUT MUXOUT options. The ispGDX240VA uses a VCCIO pin to provide B29 B28 the 2.5V reference voltage when used. B30 B29 PCI Compatible Drive Capability B31 ...
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... Decoders Buffers / Registers Data Path System Bus #2 Clock(s) Specifications ispGDX240VA Programmable Switch Replacement (PSR) Includes solid-state replacement and integration of me- chanical DIP Switch and jumper functions. Through in-system programming, pins of the ispGDXVA devices can be driven to HIGH or LOW logic levels to emulate the traditional device outputs ...
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... OE3 Port #4 OE4 Note: All OE and SEL lines driven by external arbiter logic (not shown). Specifications ispGDX240VA Designing with the ispGDXVA As mentioned earlier, this architecture satisfies the PRSI class of applications without restrictions: any I/O pin as a single input or bidirectional can drive any other I/O pin as ...
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... I/O Reference Voltage CCIO o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Dedicated Clock Capacitance 2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispGDX240VA 1 0°C to +70°C Commercial -40°C to +85°C Industrial A PACKAGE TYPE TYPICAL TQFP TQFP MINIMUM 10,000 8 MIN. MAX. ...
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... V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. Typical values are 3.3V and T CC Specifications ispGDX240VA Figure 8. Test Load GND to V CCIO(MIN) < 1.5ns 10 CCIO(MIN CCIO(MIN) See Figure 8 Device Output * C L includes Test Fixture and Probe Capacitance. ...
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... An input driving four I/O cells at 40MHz results in a dynamic I 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. Specifications ispGDX240VA Over Recommended Operating Conditions CONDITION – ...
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... Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. Specifications ispGDX240VA Over Recommended Operating Conditions DESCRIPTION 1 ...
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... External Timing Parameters (Continued) ispGDX240VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas ispGDX240VA Maximum Specifications ispGDX240VA apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1) ...
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... I/O Clock Enable (Yx Clock) ioclkeng Global Reset t 65 Global Reset to I/O Register Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX240VA 1 Over Recommended Operating Conditions 1 DESCRIPTION -10 MIN. MAX. MIN. MAX. MIN. MAX. UNITS — ...
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... Timing Model OE MUX Expander Input MUX0 MUX1 GRP tgrp #33 CLKEN tioclkeg #64 CLK tioclk #60 Y0,1,2,3 tgclk #61 Y0,1,2,3, Enable Specifications ispGDX240VA DATA (I/O INPUT) CLK REGISTERED I/O OUTPUT CLKEN t en RESET wl REGISTERED I/O OUTPUT tgoe #58 tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 MUX Expander Output ...
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... TCK EPEN ispGDX 240VA Device Specifications ispGDX240VA are fed into the on-chip programming circuitry where a state machine controls the programming. On-chip programming can be accomplished using an IEEE 1149.1 boundary scan protocol. The IEEE 1149.1- compliant interface signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS) control ...
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... Table 2. I/O Shift Register Order DEVICE TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B30 .. B59, I C59, I D29, I/O B29 .. B0, ispGDX240VA I/O A59.. A0, I/O D59 .. D30, TDO Table 3. ispGDX240VA Device ID Codes DEVICE 32-BIT BOUNDARY SCAN ID CODE ispGDX240VA 0001, 0000, 0011, 0101, 0100, 0000, 0100, 0011 Figure 7 ...
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... Figure 8. Boundary Scan State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 TCK TMS or TDI TDO tsu = 0.1µs (min.) Specifications ispGDX240VA 1 1 Select-DR-Scan Select-IR-Scan Capture-DR 0 Shift- Exit1- Pause- Exit2-DR 1 Update- 0.1µs (min.) tco = 0.1µs (min Capture-IR 0 Shift- Exit1- Pause- Exit2-IR 1 Update- ...
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... If the optional output voltage is not required, this pin must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply Connect pins are not to be connected to any active signals, VCC or GND. Signal Locations: ispGDX240VA Signal TOE L22 RESET L21 Y0/CLKEN0 ...
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... I/O A45 OE T3 I/O B35 I/O A46 MUXsel1 U1 VCC I/O A47 MUXsel2 U2 I/O B36 VCC I/O B37 I/O A48 CLK/CLKEN U3 I/O B38 Specifications ispGDX240VA Control Control Signal Ball I/O # Signal I/O B39 MUXsel2 OE V1 I/O B40 CLK/CLKEN AB15 MUXsel1 V2 I/O B41 OE MUXsel2 ...
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... I/O D36 I/O D25 OE B13 I/O D37 I/O D26 MUXsel1 A13 I/O D38 I/O D27 MUXsel2 D11 I/O D39 I/O D28 CLK/CLKEN C12 Specifications ispGDX240VA Control Control Signal Ball I/O # Signal OE B12 I/O D40 CLK/CLKEN MUXsel1 A12 I/O D41 OE MUXsel2 B11 ...
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... C19 I/O C33 I/O C57 OE C21 I/O C31 I/O C55 MUXsel2 C22 I/O C28 I/O A6 MUXsel1 D1 I/O C30 NOTE: VCC and GND Pads Shown for Reference Specifications ispGDX240VA Control Control Signal Ball I/O # Signal I/O A29 MUXsel2 D3 I/O A30 MUXsel1 MUXsel1 ...
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... Signal Configuration: ispGDX240VA ispGDX240VA 388-Ball fpBGA (1.0mm Ball Pitch / 23.0mm x 23.0mm Body Size I/O I/O I/O I/O I/O A GND C59 D12 I/O I/O I/O I/O I/O B GND C58 D11 I/O I/O I/O I/O I/O C GND C55 C57 D3 D7 D10 I/O I/O ...
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... COMMERCIAL ORDERING NUMBER ispGDX240VA-4B388 ispGDX240VA-7B388 INDUSTRIAL ORDERING NUMBER ispGDX240VA-7B388I ispGDX240VA-10B388I COMMERCIAL ORDERING NUMBER ispGDX240VA-4BN388 ispGDX240VA-7BN388 INDUSTRIAL ORDERING NUMBER ispGDX240VA-7BN388I ispGDX240VA-10BN388I 23 0212/gdx240va PACKAGE 388-Ball fpBGA 388-Ball fpBGA Table 2-0041A/gdx240va PACKAGE 388-Ball fpBGA 388-Ball fpBGA Table 2-0041/gdx240va PACKAGE Lead-Free 388-Ball fpBGA Lead-Free 388-Ball fpBGA ...