LAN9217-MT SMSC, LAN9217-MT Datasheet - Page 138

• Manufacturer Part Number: LAN9217-MT
• Description: Ethernet ICs Hi Perfrm Sngl Chip Ethrnet Contrllr
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9217-MT

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 69 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 9 Revision History
Revision 2.7 (03-15-10)
REVISION LEVEL & DATE
(03-15-10)
(10-24-08)
(07-30-08)
(08-18-08)
(06-19-08)
(06-10-08)
(11-13-08)
Rev. 2.7
Rev. 2.5
Rev. 2.4
Rev. 2.3
Rev. 2.3
Rev. 2.2
Rev. 2.2
Chapter 2, "Pin Description
and Configuration," on
page 14
Section 7.2, "Operating
Conditions**," on page 130
Section 7.2, "Operating
Conditions**," on page 130
Section 7.6, "DC Electrical
Specifications," on page 134
All
Section 3.7, "General
Purpose Timer (GP Timer),"
on page 31
Section 5.3.23, "E2P_CMD
– EEPROM Command
Register," on page 95
Table 7.7 on page 136
Block Diagram
Note 7.6 on page 135
Figure 1.2, "Internal Block
Diagram"
Auto-negotiation
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Auto-negotiation
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SECTION/FIGURE/ENTRY
Table 9.1 Customer Revision History
DATASHEET
16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support
138
Added pin 1 designator to pin diagram
Added note: “Do not drive input signals without
power supplied to the device.”
Added note: “Apply and remove power to all power
supply pins simultaneously, including the Ethernet
magnetics. Do not apply power to individual supply
pins without the others.”
Added max input capacitance numbers
Fixed various typos
Changed incorrect “GPT_CNT” reference to
“GPT_LOAD”: “On a reset, or when the
TIMER_EN bit changes from set ‘1’ to cleared ‘0,’
the GPT_LOAD field is initialized to FFFFh.”
Corrected MAC Address Loaded (bit 8) type from
“RO” to “R/WC”
Updated crystal specifications:
Drive Level: 300uW
ESR: 50 Ohms.
Figure modified removing “system memory” and
double-sided arrow on top of the “processor” block.
Note following I/O Buffer Characteristics table
modified:
Changed from: ".....the per-pin input leakage is 10
divided by the maximum input leakage current."
to: ".....the per-pin input leakage is the maximum
input leakage current divided by 10."
Diagram redone. The second PLL regulator was
added to the diagram.
The word “Core” was added to the regulator block
title.
Added note to VDD_CORE/VDD18CORE and
VDD_PLL that states “These pins must not be
used to supply power to other external devices.”
Bits 9 and 15 relabeled as Reserved, Read-Only
(RO), with a default of 0.
Fixed definition of bits 11:10 when equal to “11” by
adding “advertise support for..” to beginning of
definition. Also added note stating “When both
symmetric PAUSE and asymmetric PAUSE
support are advertised, the device will only be
configured to, at most, one of the two settings
upon auto-negotiation completion.”
CORRECTION
SMSC LAN9217
Datasheet