LAN9217-MT SMSC, LAN9217-MT Datasheet - Page 83

• Manufacturer Part Number: LAN9217-MT
• Description: Ethernet ICs Hi Perfrm Sngl Chip Ethrnet Contrllr
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9217-MT

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 69 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9217
5.3.9.1
TX_FIF_SZ
10
11
12
13
14
2
3
4
5
6
7
8
9
Allowable settings for Configurable FIFO Memory Allocation
TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above. The user
must select the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the hardware
configuration (HW_CFG) register. The TX_FIF_SZ field selects the total allocation for the TX data path,
including the TX Status FIFO size. The TX Status FIFO size is fixed at 512 Bytes (128 TX Status
DWORDs). The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder
being the TX data FIFO Size. Note that TX data FIFO space includes both commands and payload
data.
RX FIFO Size is the remainder of the unallocated FIFO space (16384 bytes – TX FIFO Size). The RX
Status FIFO size is always equal to 1/16 of the RX FIFO Size. The RX Status FIFO length is subtracted
from the total RX FIFO size with the remainder being the RX data FIFO Size.
For example, if TX_FIF_SZ = 6 then:
Total TX FIFO Size = 6144 Bytes (6KB)
TX Status FIFO Size = 512 Bytes (Fixed)
TX Data FIFO Size = 6144 – 512 = 5632 Bytes
RX FIFO Size = 16384 – 6144 = 10240 Bytes (10KB)
RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs)
RX Data FIFO Size = 10240 – 640 = 9600 Bytes
Table 5.3
are reserved and should not be used.
Note: The RX data FIFO is considered full 4 DWORDs before the length that is specified in the
HW_CFG register.
shows every valid setting for the TX_FIF_SZ field. Note that settings not shown in this table
TX DATA FIFO
SIZE (BYTES)
10752
11776
12800
13824
1536
2560
3584
4608
5632
6656
7680
8704
9728
Table 5.3 Valid TX/RX FIFO Allocations
TX STATUS FIFO
SIZE (BYTES)
DATASHEET
512
512
512
512
512
512
512
512
512
512
512
512
512
83
RX DATA FIFO
SIZE (BYTES)
13440
12480
10560
11520
9600
8640
7680
6720
5760
4800
3840
2880
1920
RX STATUS FIFO
SIZE (BYTES)
Revision 2.7 (03-15-10)
896
832
768
704
640
576
512
448
384
320
256
192
128