LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 39

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BANK 3
SMSC LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
BYTE
BYTE
BYTE
BYTE
HIGH
HIGH
LOW
LOW
OFFSET
OFFSET
FLTST - Facilitates the inclusion of packet forwarding information on the receive packet memory structure.
When 0, RD0-RD7 is always driven. When 1, RD0-RD7 is floated during RECEIVE FRAME STATUS
WORD writes (RA2-RA16=0, RCVDMA=1, nRWE0-nRWE3=0).
MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0).
MDO - MII Management output. The value of this bit drives the MDO pin.
MDI - MII Management input. The value of the MDI pin is readable using this bit.
MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.
MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-stated.
The purpose of this interface, along with the corresponding pins is to implement MII PHY management in
software.
CHIP - Chip ID. Can be used by software drivers to identify the device used.
REV - Revision ID. Incremented for each revision of a given device.
nRXDISC PIN COUNTER - 8-bit counter increments when a packet is discarded due to the nRXDISC pin
being active. This counter will be reset to 00 when read. A count of FF will set the RX_DISC INT. The
count will wrap around to 00 after FF.
RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being
received. When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will
be set to indicate that the packet was discarded. Otherwise, the packet will be received normally and bit 0
set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing.
MBO – Must be 1.
A
C
DISCR
RCV
D
0
1
0
0
REVISION REGISTER
0
0
0
0
0
RCV REGISTER
CHIP
NAME
NAME
1
0
0
0
0
DATASHEET
nRXDISC PIN COUNTER
Page 39
MBO
1
0
0
1
MBO
READ/WRITE
0
0
0
1
READ ONLY
TYPE
TYPE
MBO
0
0
0
1
REV
MBO
1
0
0
1
SYMBOL
SYMBOL
RCV
REV
Revision 1.0 (09-22-08)
MBO
1
0
0
1