LAN91C100-FD SMSC [SMSC Corporation], LAN91C100-FD Datasheet
LAN91C100-FD
Related parts for LAN91C100-FD
LAN91C100-FD Summary of contents
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... MAC-PHY Interface Running at Nibble Rate MII Management Serial Interface Seven Wire Interface to 10 Mbps ENDEC EEPROM-Based Setup Full Duplex Capability ORDERING INFORMATION Order Numbers: LAN91C100-FD for 208 Pin QFP Package Page 1 PRELIMINARY LAN91C100FD REV. D FEAST Fast Ethernet Controller with Full Duplex Capability Datasheet Rev ...
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... CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability Page 2 PRELIMINARY SMSC DS – LAN91C100FD Rev. D ...
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... Chapter 10 Package Outlines............................................................................................................. 77 Chapter 11 LAN91C100FD REV. D Revisions ................................................................................ 79 Figure 3.1 - LAN91C100FD Block Diagram .................................................................................................................13 Figure 3.2 - LAN91C100FD System Diagram ..............................................................................................................14 Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path..............................................................................18 Figure 5.1 - Data Packet Format ..................................................................................................................................19 Figure 5.2 - Interrupt Structure .....................................................................................................................................37 Figure 5.3 - Interrupt Service Routine ..........................................................................................................................45 Figure 5 INTR ...................................................................................................................................................46 Figure 5 INTR....................................................................................................................................................47 Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) ......................................................................48 SMSC DS – ...
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... Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU ....................................................................................52 Figure 6 Serial EEPROM Map...................................................................................................................55 Figure 7.1 - LAN91C100FD on VL BUS.......................................................................................................................58 Figure 7.2 - LAN91C100FD on ISA Bus.......................................................................................................................60 Figure 7.3 - LAN91C100FD on EISA Bus ....................................................................................................................63 Figure 9.1 - Asynchronous Cycle - nADS=0.................................................................................................................67 Figure 9.2 - Asynchronous Cycle - Using nADS...........................................................................................................68 Figure 9.3 - Asynchronous Cycle - nADS=0.................................................................................................................69 Figure 9.4 - Burst Write Cycles - nVLBUS=1 ...............................................................................................................70 Figure 9 ...
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... For this first generation of products, flexibility dominates over integration. The LAN91C100FD is a digital device that implements the MAC portion of the CSMA/CD protocol at 10 and 100 Mbps, and couples it with a lean and fast data and control path system architecture to ensure the CPU to packet RAM data movement does not cause a bottleneck at 100 Mbps ...
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... GND 122 D24 121 GND 120 VDD 119 D25 118 D26 117 GND 116 D27 115 D28 114 D29 113 D30 112 GND 111 D31 110 nRDYRTN 109 nLDEV 108 VDD 107 nSRDY 106 LCLK 105 SMSC DS – LAN91C100FD Rev. D ...
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... Write/ W/nR nRead 181 nVL Bus nVLBUS Access 105 Local Bus LCLK Clock SMSC DS – LAN91C100FD Rev. D BUFFER DESCRIPTION TYPE I Input. Decoded by LAN91C100FD to determine access to its registers. I Input. Used by LAN91C100FD for internal register selection. I Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. ...
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... EEPROM. I with Input. External switches can be connected to pullup these lines to select between predefined EEPROM configurations. I with Input. Enables (when high or open) pullup LAN91C100FD accesses to the serial EEPROM. Must be grounded if no EEPROM is connected to the LAN91C100FD. Page 8 PRELIMINARY SMSC DS – LAN91C100FD Rev. D ...
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... RAM. O4 Outputs. Active low signals used to write any byte, word or dword in RAM. O4 Output. This pin is active during LAN91C100FD write memory cycles of receive packets. Iclk An external 25 MHz crystal is connected across these pins TTL clock is supplied instead, it should be connected to XTAL1 and XTAL2 should be left open ...
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... Input. Transmit clock input from MII. Nibble rate pullup clock (25 MHz). This pin is ignored when MIISEL is low. I with Input. Receive clock input from MII PHY. Nibble pullup rate clock. This pin is ignored when MIISEL is low. Page 10 PRELIMINARY SMSC DS – LAN91C100FD Rev. D ...
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... DMAed to memory or if asserted during the last DMA write to memory. Works for both MII and ENDEC. The typical use of nRXDISC is with the LAN91C100FD in PRMS mode with an external associative memory use for address filtering. *Note: The pin must be asserted for a minimum of 80ns. ...
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... TXEN, TXD, CRS, COL, RXD, TXC, RXC, LBK, nLNK, nFSTEP, AUISEL, MIISEL TXEN100, CRS100, COL100, RX_DV, RX_ER, TXD0-TXD3, RXD0-RXD3, MDI, MDO, MCLK TX25, RX25 nCSOUT, nRXDISC Page 12 PRELIMINARY NUMBER OF PINS 205 SMSC DS – LAN91C100FD Rev. D ...
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... SERIAL EEPROM Address BUS Data INTERFACE UNIT Control RD WR FIFO FIFO SMSC DS – LAN91C100FD Rev. D ARBITER DIRECT MEMORY ACCESS MEMORY MANAGEMENT UNIT RAM 25 MHz Figure 3.1 - LAN91C100FD Block Diagram Page 13 PRELIMINARY 10 Mb Interface MEDIA 100 Media ACCESS Independent Interface CONTROL Rev. 10/14/2002 ...
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... SYSTEM BUS ADDRESS ADDRESS CONTROL CONTROL DATA DATA RA Figure 3.2 - LAN91C100FD System Diagram Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability SERIAL EEPROM 1O Mbps LAN91C100FD FEAST MII OE,WE RD0-31 OR SRAM 3 4 32kx8 2 1 Page 14 PRELIMINARY LAN83C69 10BASE-T 10BASE-T INTERFACE 100BASE-T4 INTERFACE ...
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... The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU requests represent pipelined CPU accesses to the Data Register, while DMA requests represent CSMA/CD data movement. The external memory used is a 25ns SRAM. SMSC DS – LAN91C100FD Rev. D Page 15 PRELIMINARY ...
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... For the MII interface, transmit data is clocked out using the TX25 clock input, while receive data is clocked in using RX25. In 100 Mbps mode, the LAN91C100FD provides the following interface signals to the PHY: For transmission: TXEN100 TXD0-3 TX25 For reception: RX_DV RX_ER RXD0-3 RX25 ...
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... Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The LAN91C100FD will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a timeout on TX25 is detected. ...
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... EEPROM EEPROM INTERFACE DATA BUS ADDRESS BUS BUS INTERFACE CONTROL WRITE DATA REG Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability RX TX FIFO DMA FIFO TX COMPL FIFO ARBITER READ DATA REG ...
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... BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant. SMSC DS – LAN91C100FD Rev. D STATUS reserved BYTE ...
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... CPU, including the source address. The LAN91C100FD does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C100FD treated transparently as data both for transmit and receive operations. ...
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... Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. Regardless of the functional description, all registers can be accessed as doublewords, words or bytes. SMSC DS – LAN91C100FD Rev. D HASH VALUE 5-0 000 000 ...
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... BANK7 is selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of external registers. Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done if the Revision Control register indicates the device is the LAN91C100FD. Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability Table 5.1 - Internal I/O Space Mapping ...
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... CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C100FD will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation. ...
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... LOOP - Loopback. General purpose output port used to control the LBK pin. Typically used to put the PHY chip in loopback mode. TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C100FD will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. BANK 0 ...
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... SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C100FD’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). ...
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... NUMBER OF DEFFERED SINGLE COLLISION COUNT NAME TYPE READ ONLY REGISTER FREE MEMORY AVAILABLE (IN BYTES * 256 * MEMORY SIZE (IN BYTES *256 * Page 26 PRELIMINARY SYMBOL ECR SYMBOL MIR SMSC DS – LAN91C100FD Rev. D ...
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... The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the Memory Size Multiplier. M=2 for the LAN91C100FD. A value of 04h in the lower byte of the MCR is equal to one 2K page (4 * 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only when the entire memory is being reserved for transmit (i ...
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... INT SEL1-0 - Used to select one out of four interrupt pins. The three unused interrupts are tristated. INT SEL1 BANK 1 OFFSET 2 BASE ADDRESS REGISTER This register holds the I/O address decode option chosen for the LAN91C100FD part of the EEPROM saved setup and is not usually modified during run-time. HIGH A15 A14 BYTE ...
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... Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C100FD. BANK 1 OFFSET C CONTROL REGISTER HIGH 0 RCV_ BAD BYTE 0 0 LOW LE CR BYTE ENABLE ENABLE 0 0 SMSC DS – LAN91C100FD Rev. D ADDRESS ADDRESS ADDRESS ADDRESS ...
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... During this time attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C100FD after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750 µs. ...
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... Namely N2,N1, will request 2 * 256 = 512 bytes. A shift-based divide by 256 of the packet length yields the appropriate value to be used as N2,N1,N0. Immediately generates a completion code at the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. N2,N1,N0 are ignored by the LAN91C100FD but should be implemented in LAN91C100FD software drivers for LAN9000 compatibility. 010 2) RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts, resets packet FIFO pointers ...
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... Notes: Bits N2,N1,N0 bits are ignored by the LAN91C100FD but should be used for command 0 to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands. When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them ...
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... When RCV is set the address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address refers to the transmit area and uses the packet number at the Packet Number Register. SMSC DS – LAN91C100FD Rev. D NAME TYPE ...
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... This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C100FD regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers ...
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... Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register ENABLE (Link Error Enable ENABLE (Counter Roll Over ENABLE (Transmit Error Enable) EPH INT will only be cleared by the following methods: SMSC DS – LAN91C100FD Rev. D NAME WRITE ONLY REGISTER ...
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... FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. The Receive Interrupt is cleared when RX FIFO is empty. Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability Page 36 PRELIMINARY SMSC DS – LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability SMSC DS – LAN91C100FD Rev. D Figure 5.2 - Interrupt Structure Page 37 PRELIMINARY Rev. 10/14/2002 ...
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... MULTICAST TABLE MULTICAST TABLE NAME TYPE READ/WRITE MDOE Page 38 PRELIMINARY SYMBOL SYMBOL MGMT MCLK MDI MDO 0 MDI Pin 0 SMSC DS – LAN91C100FD Rev. D ...
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... ERCV THRESHOLD - Threshold for ERCV interrupt. Specified in 64 byte multiples. Whenever the number of bytes written in memory for the presently received packet exceeds the ERCV THRESHOLD, ERCV INT bit of the INTERRUPT STATUS REGISTER is set. SMSC DS – LAN91C100FD Rev. D NAME TYPE READ ONLY ...
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... BANK7 OFFSET 0 THROUGH 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C100FD when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE CYCLE AEN=0 A3=0 A4-15 matches I/O BASE BANK SELECT = 7 BANK SELECT = 4,5,6 Otherwise Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability ...
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... Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again. SMSC DS – LAN91C100FD Rev. D The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state ...
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... Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability Page 42 PRELIMINARY SMSC DS – LAN91C100FD Rev. D ...
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... Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again. SMSC DS – LAN91C100FD Rev. D The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state ...
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... If the CRC checks correctly the packet number is written into the RX FIFO. The RX FIFO, being not empty, causes RCV INT (interrupt set. If CRC is incorrect the packet memory is released and no interrupt will occur. Page 44 PRELIMINARY MAC SIDE SMSC DS – LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability Call TX INTR or TXEMPTY INTR Get Next TX Packet Available for Transmission? Yes Call ALLOCATE Call EPH INTR SMSC DS – LAN91C100FD Rev. D ISR Save Bank Select & Address Ptr Registers Mask SMC91C100FD Interrupts Read Interrupt Register No Yes TX INTR? ...
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... Address No Yes Filtering Pass? No Yes Status Word OK? Do Receive Lookahead Get Copy Specs from Upper Layer Okay to No Yes Copy? Copy Data Per Upper Layer Specs Issue "Remove and Release" Command Return to ISR Figure 5 INTR Page 46 PRELIMINARY SMSC DS – LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability SMSC DS – LAN91C100FD Rev INTR Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register Read Status Word from RAM Yes No TX Status OK? Immediately Issue " ...
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... Failed) Read Pkt. # Register & Save Write Address Pointer Register Read Status Word from RAM Update Statistics Issue "Release" Command Acknowledge TXINTR Re-Enable TXENA Restore Packet Number Return to ISR Page 48 PRELIMINARY TXEMPTY = 1 & TXINT = 0 successfully) Update Variables SMSC DS – LAN91C100FD Rev. D ...
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... Memory Partitioning Unlike other controllers, the LAN91C100FD does not require a fixed memory partitioning between transmit and receive resources. The MMU allocates and de-allocates memory upon different events. An additional mechanism allows the CPU to prevent the receive process from starving the transmit memory allocation. ...
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... If the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. Note that with the memory management built into the LAN91C100FD, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory) ...
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... In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX DONE PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C100FD and provided back to the CPU as their transmission completes. ...
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... Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability PACKET NUMBER REGISTER 'EMPTY' TX DONE CPU ADDRESS PACK # OUT Page 52 PRELIMINARY 'NOT EMPTY' RX FIFO PACKET NUMBER RX PACKET NUMBER CSMA ADDRESS SMSC DS – LAN91C100FD Rev. D ...
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... IOS jumpers. In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C100FD. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, INTERRUPT) that can always be used regardless of the EEPROM based value being programmed ...
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... RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until read low is used to determine completion. When an EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C100FD can be read or written until the EEPROM operation completes and both bits are clear. ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability IOS2-0 000 001 010 011 100 101 110 XXX SMSC DS – LAN91C100FD Rev. D WORD ADDRESS 0h CONFIGURATION REG. 1h BASE REG. 4h CONFIGURATION REG. 5h BASE REG. 8h CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. Dh BASE REG. 10h CONFIGURATION REG. ...
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... VL Local Bus 32 Bit Systems On VL Local Bus and other 32 bit embedded systems the LAN91C100FD is accessed bit peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions. ...
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... GND A1 nVLBUS OPEN nDATACS SMSC DS – LAN91C100FD Rev. D NOTES Byte enables. Latched transparently by nADS rising edge. Address Strobe is connected directly to the VL bus. nCYCLE is created typically by using nADS delayed by one LCLK. Typically uses the interrupt lines on the ISA edge connector of VL bus 32 bit data bus ...
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... LCLK nLRDY nLDEV Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability W/nR A2-A15 LCLK AEN RESET LAN91C100FD INTR0-INTR3 D0-D31 nRDYRTN nBE0-nBE3 nADS nCYCLE nSRDY O.C. simulated O.C. Figure 7.1 - LAN91C100FD on VL BUS Page 58 PRELIMINARY nLDEV SMSC DS – LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability 7.3 High End ISA or Non-Burst EISA Machines On ISA machines, the LAN91C100FD is accessed bit peripheral. No support for XT (8 bit peripheral) is provided. The signal connections are listed in the following table: Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors ...
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... RESET VCC D0-D15 nIRQ nIORD nIOWR A0 nSBHE nIOCS16 Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability A1-A15, AEN RESET nBE2, nBE3 D0-D15 LAN91C100FD INTR0-INTR3 nRD nWR nBE0 nBE1 nLDEV O.C. Figure 7.2 - LAN91C100FD on ISA Bus Page 60 PRELIMINARY SMSC DS – LAN91C100FD Rev. D ...
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... EISA 32 Bit SLAVEEISA 32 Bit Slave On EISA the LAN91C100FD is accessed bit I/O slave, along with a Slave DMA type "C" data path option I/O slave, the LAN91C100FD uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is externally derived from nCMD edges. Given that the access will be at least 1 ...
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... BCLK wide). EISA Bus Clock. Data transfer clock for DMA bursts. DMA Acknowledge. Active during Slave DMA cycles. Used by the LAN91C100FD as nDATACS direct access to data path. Indicates the direction and timing of the DMA cycles. High during LAN91C100FD writes, low during LAN91C100FD reads ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability EISA BUS LA2-LA15 RESDRV AEN M/nIO D0-D31 IRQn nBE0-nBE3 nCMD LATCH + gates nWR BCLK nSTART nEX32 SMSC DS – LAN91C100FD Rev. D A2-A15 RESET AEN D0-D31 INTR0-INTR3 LAN91C100FD nBE0-nBE3 nRD nWR LCLK nADS nLDEV O.C. Figure 7.3 - LAN91C100FD on EISA Bus Page 63 PRELIMINARY Rev. 10/14/2002 ...
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... High Input Level Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability SYMBOL MIN TYP MAX V 0.8 ILI 2.0 V IHI V 0.8 ILIS 2.2 V IHIS V 250 HYS V 0.4 ILCK V 3.0 IHCK Page 64 PRELIMINARY + 0.3V CC UNITS COMMENTS V TTL Levels V V Schmitt Trigger V Schmitt Trigger SMSC DS – LAN91C100FD Rev. D ...
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... O12 Type Buffer Low Output Level High Output Level Output Leakage O16 Type Buffer Low Output Level High Output Level Output Leakage OD16 Type Buffer Low Output Level Output Leakage SMSC DS – LAN91C100FD Rev. D SYMBOL MIN TYP MAX I -10 + -10 ...
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... PRELIMINARY UNITS COMMENTS - µ - µ All Outputs Open UNIT TEST CONDITION pF All pins except pin under test tied to AC ground pF pF SMSC DS – LAN91C100FD Rev. D ...
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... A1-A15, AEN, nBE0-nBE3 Hold After nRD, nWR Inactive (Assuming nADS Tied Low) t3 nRD Low to Valid Data t4 nRD High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive SMSC DS – LAN91C100FD Rev. D A1-15, AEN, nBE0-nBE3 valid t3 t1 D0-D31 valid PARAMETER Page 67 PRELIMINARY t2 t4 ...
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... A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold after nADS Rising Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability D0-D31 valid PARAMETER Page 68 PRELIMINARY t4 t5A MIN TYP MAX UNITS SMSC DS – LAN91C100FD Rev. D ...
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... A1-A15, AEN, nBE0-nBE3 Hold After nRD, nWR Inactive (Assuming nADS Tied Low) t3 nRD Low to Valid Data t4 nRD High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive SMSC DS – LAN91C100FD Rev D0-D31 valid PARAMETER Page 69 PRELIMINARY ...
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... Data Hold from LCLK Rising (Write) Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability t12 t17 t20 t18 a b PARAMETER Page 70 PRELIMINARY t13 t17 c t15 t14 MIN TYP MAX UNITS SMSC DS – LAN91C100FD Rev. D ...
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... Hold after Either nCYCLE or W/nR Rising t14 nRDYRTN Setup to LCLK Falling t15 nRDYRTN Hold after LCLK Falling t17 nCYCLE High and W/nR High Overlap t19 Data Delay from LCLK Rising (Read) Note 9.1 (holdt.) Note 9.2 (Setupt.) SMSC DS – LAN91C100FD Rev. D t12 t17 t19 a b t15 t14 MIN ...
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... MIN t9 A1-A15, AEN, nBE0-nBE3 t8 t16 PARAMETER Page 72 PRELIMINARY t9 TYP MAX UNITS t18 t20 t17A t11 t10 D0-D31 valid t21 t21 MIN TYP MAX UNITS SMSC DS – LAN91C100FD Rev. D ...
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... W/nR Setup to nCYCLE Active t20 Data Hold from LCLK Rising (Read) t21 nLRDY Delay from LCLK Rising t23 nRDYRTN Setup to LCLK Rising t24 nRDYRTN Hold after LCLK Rising SMSC DS – LAN91C100FD Rev A1-A15, AEN, nBE0-nBE3 t8 t10 t16 t11 PARAMETER Page 73 PRELIMINARY ...
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... MULTIPLE READ CYCLES Figure 9.9 - SRAM Interface Page 74 PRELIMINARY t50 t50 t51 t52 t53 READ CYCLE t50 t50 t35 t39 t39 t36 t37 t51 t38 t38 MIN TYP MAX UNITS SMSC DS – LAN91C100FD Rev. D ...
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... RXD Hold After RXC Rising Notes: 1. CRS input might be asynchronous to RXC. 2. RXC starts after CRS goes active. RXC stops after CRS goes inactive. 3. COL is an asynchronous input. SMSC DS – LAN91C100FD Rev. D t30 Figure 9.10 - ENDEC Interface - 10 Mbps MIN TYP Page 75 ...
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... RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising Rev. 10/14/2002 FEAST Fast Ethernet Controller with Full Duplex Capability t27 t27 Figure 9.11 - MII Interface MIN Page 76 PRELIMINARY t28 t28 t28 t29 t29 TYP MAX UNITS SMSC DS – LAN91C100FD Rev. D ...
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... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC DS – LAN91C100FD Rev. D MAX 4.07 Overall Package Height 0.5 3.67 Body Thickness 30 ...
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... Overall Package Height 0.15 1.45 Body Thickness 30.20 28.10 30.20 28.10 0.23 Lead Frame Thickness 0.75 Lead Foot Length ~ o 7 Lead Foot Angle 0.27 ~ Lead Shoulder Radius 0.20 Lead Foot Radius 0.08 Page 78 PRELIMINARY REMARK Standoff X Span X Body Size Y Span Y body Size Lead Length Lead Pitch Lead Width Coplanarity SMSC DS – LAN91C100FD Rev. D ...
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... Pin Functions 23 Table under Bank Electrical and Timing Section SMSC DS – LAN91C100FD Rev. D CORRECTION Modified the description of the FDUPLX bit and the PAD_EN bit Modified the description of the Interrupt Register bits Modified the interrupt structure figure Modified the Transmit Flow Routine ...