LAN91C96-MS SMSC, LAN91C96-MS Datasheet - Page 81

• Manufacturer Part Number: LAN91C96-MS
• Description: Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C96-MS

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 95 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
9.5
SMSC LAN91C96 5v&3v
If the access time is the problem, IOCHRDY should be negated for all accesses to the LAN91C96. This
can be achieved by programming the NO WAIT ST bit in the configuration register to “0”. The LAN91C96
will negate IOCHRDY for 100ns to 150ns on every access to any register.
If the cycle time is the problem, programming NO WAIT ST as described before will solve it but at the
expense of slowing down all accesses. The alternative is to let the LAN91C96 negate IOCHRDY only
when the Data Register FIFOs require so. Namely, if NO WAIT ST is set, IOCHRDY will only be negated if
a Data Register read cycle starts and there is less than a full word in the read FIFO, or if a write cycle
starts and there is more than two bytes in the write FIFO.
The cycle time is defined as the time between leading edges of read from the Data Register, or
equivalently between trailing edges of write to the Data Register. For example, in an LOCAL BUS system
the cycle time of a 16 bit transfer will be at least 2 clocks for the I/O access to the LAN91C96 (+ one clock
for the memory cycle) for a total of 3 clocks. In absolute time it means 375ns for an 8MHz bus, and 240ns
for a 12.5 MHz bus.
The cycle time will not increase when configured for full duplex mode, because the CSMA/CD memory
arbitration requests are sequenced by the DMA logic and never overlap.
Arbitration Considerations
The arbiter exploits the sequential nature of the CPU accesses to provide a very fast access time. Memory
bandwidth considerations will have an effect on the CPU cycle time but no effect on access time.
For normal 8MHz, 10MHz, and 12.5MHz LOCAL BUS, as well as EISA normal cycles, the LAN91C96 can
be accessed without negating ready.
When write operations occur, the data is written into a FIFO. The CPU cycle can complete immediately,
and the buffered data will be written into memory later. The memory arbitration request is generated as a
function of that FIFO being not empty. The nature of the cycle requested (byte/word) is determined by the
LSB of the pointer and the number of bytes in the FIFO.
When read operations occur, words are pre-fetched upon pointer loading in order to have at least a word
ready in the FIFO to be read. New pre-fetch cycles are requested as a function of the number of bytes in
the FIFO.
For example, if an odd pointer value is loaded, first a byte is pre-fetched into the FIFO, and immediately a
full word is pre-fetched completing three bytes into the FIFO. If the CPU reads a word, one byte will be left
again a new word is pre-fetched.
In the case of write, if an odd pointer value is loaded, and a full word is written, the FIFO holds two bytes,
the first of which is immediately written into an odd memory location. If by that time another byte or word
was written, there will be two or three bytes in the FIFO and a full word can be written into the now even
memory address.
When a CSMA/CD cycle begins, the arbiter will route the CSMA/CD DMA addresses to the MMU as well
as the packet number associated with the operation in progress. In full-duplex mode, receive and transmit
requests are alternated in such a way that the CPU arbitration cycle time is not affected.
DATASHEET
Page 81
Revision 1.0 (10-24-08)