LAN9215I-MT SMSC, LAN9215I-MT Datasheet - Page 121

• Manufacturer Part Number: LAN9215I-MT
• Description: Ethernet ICs Indust Hi Efficient Single-Chip
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9215I-MT

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 69 mA
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
SMSC LAN9215i
6.1.2
RX Status FIFO
TX Status FIFO
RX Data FIFO
RX_DP_CTRL
READING...
RX_DROP
AFTER
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9215i, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met.
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
Note 6.1
This restriction is only applicable after a fast-forward operation has been completed and
the RX_FFWD bit has been cleared. Refer to
Forward," on page 57
WAIT FOR THIS MANY
NS…
165
165
165
330
330
Table 6.2 Read After Read Timing Rules
for more information.
DATASHEET
Table 6.2
121
OR PERFORM THIS MANY
READS OF BYTE_TEST…
(ASSUMING Tcycle OF
Table 6.2, "Read After Read Timing
also shows the number of dummy reads that are
165NS)
1
1
1
2
2
Section 3.13.1.1, "Receive Data FIFO Fast
BEFORE READING...
RX Status FIFO
TX Status FIFO
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
RX_DROP
Note 6.1
Revision 2.7 (03-15-10)
Rules". The host