LAN9500A-ABZJ SMSC, LAN9500A-ABZJ Datasheet - Page 15

• Manufacturer Part Number: LAN9500A-ABZJ
• Description: Ethernet ICs Hi-Speed USB 2.0 10/100 Ethernet CTRL
• Manufacturer: SMSC

Specifications of LAN9500A-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB 2.0 to 10/100 Ethernet Controller
Datasheet
SMSC LAN950x Family
NUM PINS
1
1
1
Note 3.1
Transmit Data
Purpose I/O 5
Transmit Data
Purpose I/O 4
(Internal PHY
(Internal PHY
Configuration
Configuration
PHY Mode)
Mode Only)
PHY Mode)
Mode Only)
PHY Mode)
EEPROM
(External
(External
(External
Transmit
General
Wakeup
General
Remote
Disable
NAME
Clock
Strap
Strap
1
0
Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
EEP_DISABLE
RMT_WKP
SYMBOL
Table 3.1 MII Interface Pins (continued)
TXCLK
GPIO5
GPIO4
TXD1
TXD0
DATASHEET
BUFFER
IS/O8/
IS/O8/
TYPE
(PD)
OD8
(PU)
(PD)
(PD)
OD8
(PU)
(PD)
(PU)
O8
O8
IS
IS
IS
15
In external PHY mode, this pin functions as the
transmit data 1 output to the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
This strap configures the default descriptor
values to support remote wakeup.
0 = Remote wakeup is not supported.
1 = Remote wakeup is supported.
See
configuration straps.
In external PHY mode, this pin functions as the
transmit data 0 output to the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
This strap disables the autoloading of the
EEPROM contents. The assertion of this strap
does not prevent register access to the
EEPROM.
0 = EEPROM is recognized if present.
1 = EEPROM is not recognized even if it is
present.
See
configuration straps.
In external PHY mode, this pin is the transmitter
clock input from the external PHY. In internal
PHY mode, this pin is not used.
Note 3.1
Note 3.1
for more information on
for more information on
DESCRIPTION
Revision 1.0 (05-17-10)