DS3141N Maxim Integrated Products, DS3141N Datasheet - Page 48

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DS3141N

Manufacturer Part Number
DS3141N
Description
Network Controller & Processor ICs Single/Dual/Triple/Q /Quad DS3/E3 Framers
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3141N

Product
Framer
Number Of Transceivers
1
Data Rate
2.048 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
90 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3141N
Manufacturer:
Maxim Integrated
Quantity:
10 000
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7: Alternating Word Count Rate (AWC[7:0]). When the BERT is programmed in the alternating word
mode, it transmits the word in register RP[15:0] a number of times equal to AWC[7:0] + 1 and then transmits the
word loaded in RP[31:16] the same number of times. The valid count range is from 00h to FFh. These bits are
ignored if the BERT is programmed for a pseudorandom pattern or a repetitive pattern.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Synchronization Status (SYNC). This real-time status bit is set when the incoming pattern matches for 32
consecutive bit positions. SYNC bit is cleared when six or more bits out of 64 are received in error.
Bit 1: BERT Error-Counter Overflow (BECO). This real-time status bit is set when the 24-bit BERT error counter
(BEC) saturates. BECO is cleared when BCR1:LC is toggled to load the error counts.
Bit 2: BERT Bit-Counter Overflow (BBCO). This real-time status bit is set when the 32-bit BERT bit counter
(BBC) saturates. BBCO is cleared when BCR1:LC is toggled to load the error counts.
Bit 4: Receive All Zeros (RA0). This real-time status bit is set when 32 consecutive 0s are received. RA0 is
cleared when a 1 is received.
Bit 5: Receive All Ones (RA1). This real-time status bit is set when 32 consecutive 1s are received. RA1 is
cleared when a 0 is received.
AWC VALUE
FFh
00h
01h
02h
.
.
.
AWC7
N/A
7
0
Send the word in RP[15:0] 1 time followed by the word in RP[31:16] 1 time…
Send the word in RP[15:0] 2 times followed by the word in RP[31:16] 2 times…
Send the word in RP[15:0] 3 times followed by the word in RP[31:16] 3 times…
Send the word in RP[15:0] 256 times followed by the word in RP[31:16] 256 times…
7
.
.
.
AWC6
N/A
6
0
6
BCR4
BERT Control Register 4
33h
BSR
BERT Status Register
38h
AWC5
ALTERNATING COUNT ACTION
RA1
5
0
5
48 of 88
AWC4
RA0
0
4
4
AWC3
N/A
3
0
3
AWC2
BBCO
2
0
2
AWC1
BECO
1
0
1
AWC0
SYNC
0
0
0

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