DS3141N Maxim Integrated Products, DS3141N Datasheet - Page 61

• Manufacturer Part Number: DS3141N
• Description: Network Controller & Processor ICs Single/Dual/Triple/Q /Quad DS3/E3 Framers
• Manufacturer: Maxim Integrated Products

Specifications of DS3141N

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 90 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: After the RHDLC2 register is read, the receive FIFO read pointer advances and both the RHDLC1 and RHDLC2 registers are updated
with the next data/status from the receive FIFO. The host processor should read RHDLC1 first to retrieve the FIFO data and then immediately
read RHDLC2 to retrieve the associated FIFO status bits.
Bits 0 to 7: Receive FIFO Data (D[7:0]). These bits contain the next byte of receive FIFO data. D0 is the LSB and
is the first bit received by the framer, while D7 is the MSB and is the last bit received. Reading this register does
not cause the receive FIFO read pointer to advance.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Opening Byte Indicator (OBYTE). This bit is set to 1 when the RHDLC1 register contains the first byte of an
HDLC packet.
Bit 1: Closing Byte Indicator (CBYTE). This bit is set to 1 when the RHDLC1 register contains the last byte of an
HDLC packet, whether the packet is valid or not. The host processor can check the PS[1:0] bits to determine
packet validity.
Bits 2, 3: Packet Status (PS[1:0]). These bits are only valid when the CBYTE bit is set to 1. These bits indicate
the validity of the incoming packet and the cause of the problem if the packet was received in error.
Packets fewer than four bytes long (including the FCS) are invalid and the data that appears in the FIFO in such
instances is meaningless. If only one byte is received between flags, then both the CBYTE and OBYTE bits are
set. If two bytes are received, then OBYTE is set for the first byte received and CBYTE is set for the second byte
received. If three bytes are received, then OBYTE is set for the first byte received and CBYTE is set for the third
byte received. In all of these cases, the packet status is reported as PS[1:0] = 10, and the data in the FIFO should
be ignored.
PS[1:0]
00
01
10
11
PACKET STATUS
D7
N/A
—
7
—
7
Invalid
Invalid
Invalid
Valid
D6
N/A
—
6
—
6
—
Corrupt CRC
Incoming packet was either too short (less than 4 bytes including the CRC)
or did not contain an integral number of octets
Abort sequence detected
RHDLC1
Receive HDLC FIFO Data
5Ch
RHDLC2
Receive HDLC FIFO Status
5Dh
REASON FOR INVALID RECEPTION OF THE PACKET
N/A
D5
—
—
5
5
61 of 88
N/A
D4
—
—
4
4
PS1
D3
—
—
3
3
PS0
D2
—
—
2
2
CBYTE
D1
—
—
1
1
OBYTE
D0
—
—
0
0