DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 15

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

4.10 Trail Trace Buffer Features
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4.11 Bit Error-Rate Tester (BERT) Features
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4.12 Loopback Features
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4.13 Microprocessor Interface Features
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4.14 Slave Serial Peripheral Interface (SPI) Features
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4.15 Test Features
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Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register
Insertion of the outgoing trail access point identifier from a 16-byte transmit register
Receive trace identifier unstable status indication
Generates and detects pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
Supports pattern insertion/extraction in DS3/E3 payload, or entire data stream
Large 24-bit error counter allows testing to proceed for long periods without host intervention
Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
Off-line monitoring on the Receive BERT
LIU terminal loopback (transmit to receive) - ALB
Line facility loopback (receive to transmit) with optionally transmitting unframed all-one payload toward
system/trunk interface - LLB
Framer diagnostic loopback (transmit to receive) with optionally transmitting unframed all-one signal toward
line/tributary interface - DLB
Simultaneous line facility loopback (LLB) and framer diagnostic loopback (DLB)
Framer payload loopback (receive to transmit) with optionally transmitting unframed all-one payload toward
system/trunk interface - PLB
Multiplexed or nonmultiplexed 8- or 16-bit control port
Intel and Motorola bus compatible
Global reset input pin
Global interrupt output pin
Eight programmable I/O pins (GPIOx)
Three-wire synchronous serial data link operating in full duplex slave mode up to 10 Mbps
Glueless connection and fully compliant to Motorola popular communication processors such as MPC8260 and
microcontrollers such as M68HC11
Software provision ability for active phase of the serial clock (i.e. rising edge versus falling edge), bit ordering of
the serial data (most significant first versus least significant bit first)
Five pin JTAG port
All functional pins are inout pins in JTAG mode
Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
Custom JTAG instructions to use RAM BIST
RAM BIST on all internal RAM
HIZ pin to force all digital output and inout pins into HIZ
TEST pin for manufacturing scan test modes
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DS3170 DS3/E3 Single-Chip Transceiver