DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 28

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

TNEG
TXP
TXN
RXP
RXN
RLCLK
PIN NAME
TYPE
Oa
Oa
Ia
Ia
O
I
Transmit Negative AMI / Line OH Mask
TNEG: When the port line is configured for B3ZS, HDB3 or AMI mode and the
transmit line interface pins are enabled
indicates that a negative pulse should be transmitted on the line. The signal is
updated on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TLCLK line clock output pins, but it can be referenced to
the TCLKO, TCLKI, RLCLK or RCLKO pins.
This output signal can be inverted.
o
o
Transmit Positive Analog
TXP: This pin and the TXN pin form a differential AMI output which is coupled to the
outbound 75Ω coaxial cable through a 2:1 step-down transformer
output is enabled when the TX LIU is enabled and the output is enabled to be driven.
When it is not enabled, it is in a high impedance state.
o
o
Transmit Negative Analog
TXN: This pin and the TXP pin form a differential AMI output which is coupled to the
outbound 75Ω coaxial cable through a 2:1 step-down transformer
output is enabled when the TX LIU is enabled and the output is enabled to be driven.
When it is not enabled, it is in a high impedance state.
o
o
Receive Positive analog
RXP: This pin and the RXN pin form a differential AMI input which is coupled to the
outbound 75Ω coaxial cable through a 2:1 step-up transformer
is used when the RX LIU is enabled and is ignored when the LIU is disabled.
o
o
Receive Negative analog
RXN: This pin and the RXP pin form a differential AMI input which is coupled to the
outbound 75Ω coaxial cable through a 2:1 step-up transformer
is used when the LIU is enabled and is ignored when the LIU is disabled.
o
o
Receive Line Clock Input
RLCLK: This clock is typically used for the reference clock for the RPOS / RDAT,
RNEG / RLCV signals but can also be used as the reference clock for the RSER,
RSOFO / RDEN, TSOFI, TSER, TSOFO / TDEN, TPOS / TDAT and TNEG signals.
This input is ignored when the LIU is enabled.
This input signal can be inverted.
o
o
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
28 of 230
PIN DESCRIPTION
(PORT.CR2.
DS3170 DS3/E3 Single-Chip Transceiver
TLEN), a high on this pin
(Figure
(Figure
(Figure
(Figure
2-1). This input
2-1). This input
2-1). This
2-1). This