DS3154 Maxim Integrated Products, DS3154 Datasheet - Page 40

• Manufacturer Part Number: DS3154
• Description: Network Controller & Processor ICs Quad DS3-E3-STS-1 Li ne Interface Unit ST
• Manufacturer: Maxim Integrated Products

Specifications of DS3154

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 51.840 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TE-CSBGA

Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes
(V
Table 13-G. Transmitter Output Characteristics—E3 Mode
(V
Note 17: Measured on the line side (i.e., the BNC connector side) of the 2:1 transmit transformer
Note 18: Measured with jitter-free clock applied to TCLK and a bandpass jitter filter with 10Hz and 800kHz cutoff frequencies. Not tested during
Table 13-H. CPU Bus Timing
(
Note 19: D[7:0] loaded with 50pF when tested as outputs.
Note 20: If a gapped clock is applied on TCLK and diagnostic loopback is enabled, read cycle time must be extended by the length of the
Note 21: Not tested during production test.
Note 22: In nonmultiplexed bus applications
V
DS3 Output Pulse Amplitude, TLBO = 0 (Note 17)
DS3 Output Pulse Amplitude, TLBO = 1 (Note 17)
STS-1 Output Pulse Amplitude, TLBO = 0 (Note 17)
STS-1 Output Pulse Amplitude, TLBO = 1 (Note 17)
Ratio of Positive and Negative Pulse-Peak Amplitudes
DS3 Unframed All-Ones Power Level at 22.368MHz, 3kHz Bandwidth
DS3 Unframed All-Ones Power Level at 44.736MHz vs. Power Level at
22.368MHz, 3kHz Bandwidth
Intrinsic Jitter Generation (Note 18)
Output Pulse Amplitude (Note 17)
Pulse Width
Ratio of Positive and Negative Pulse Amplitudes (at Centers of Pulses)
Ratio of Positive and Negative Pulse Widths (at Nominal Half Amplitude)
Intrinsic Jitter Generation (Note 18)
Setup Time for A[5:0] Valid to CS Active (Notes 19, 20)
Setup Time for CS Active to RD, WR, or DS Active
Delay Time from RD or DS Active to D[7:0] Valid
Hold Time from RD or WR or DS Inactive to CS Inactive
Delay from CS or RD or DS Inactive to D[7:0] Invalid or Tri-State
(Note 21)
Wait Time from WR or DS Active to Latch D[7:0]
D[7:0] Setup Time to WR or DS Inactive
D[7:0] Hold Time from WR or DS Inactive
A[5:0] Hold Time from WR or RD or DS Inactive
RD, WR, or DS Inactive Time
Muxed Address Valid to ALE Falling (Note 22)
Muxed Address Hold Time (Note 22)
ALE Pulse Width (Note 22)
Setup Time for ALE High or Muxed Address Valid to CS Active
(Note 22)
DD
DD
DD
= 3.3V ±5%, T
= 3.3V ±5%, T
= 3.3V ±5%, T
production test.
should be wired to D[5:0] and the falling edge of ALE latches the address.
largest TCLK gap.
A
A
A
= -40°C to +85°C.)
= -40°C to +85°C.)
= -40°C to +85°C.
PARAMETER
PARAMETER
PARAMETER
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
(Figure
) (
Figure 13-3
13-3), ALE should be wired high. In multiplexed bus applications
40 of 61
and
Figure
13-4)
SYMBOL
t10
t11
t12
t13
t14
t1
t2
t3
t4
t5
t6
t7
t8
t9
(Figure
0.95
0.95
MIN
-1.8
MIN
MIN
700
520
700
520
900
0.9
65
10
75
10
10
30
0
0
0
2
2
5
0
1-1).
14.55
1000
TYP
0.02
TYP
0.02
TYP
800
700
800
700
(Figure
MAX
1100
MAX
1100
MAX
+5.7
0.05
1.05
1.05
0.05
900
800
850
-20
1.1
65
20
13-4), A[5:0]
UNITS
UNITS
UNITS
mVpk
mVpk
mVpk
mVpk
mVpk
dBm
UI
UI
dB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
P-P
P-P