CS61584A-IL3 Cirrus Logic Inc, CS61584A-IL3 Datasheet - Page 28
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CS61584A-IL3
Manufacturer Part Number
CS61584A-IL3
Description
Network Controller & Processor ICs IC 3.3V/5V Dul T1/E1 Line Intrfc Unit
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS61584A-IQ3Z.pdf
(54 pages)
Specifications of CS61584A-IL3
Product
Framer
Number Of Transceivers
2
Data Rate
2.048 Mbps
Supply Voltage (max)
3.465 V, 5.25 V
Supply Voltage (min)
3.135 V, 4.75 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
PLCC-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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sate for waveform degradation that may result from
non-standard cables, transformers, or protection
circuitry.
Arbitrary waveform generation is enabled when the
CON[3:0] line configuration selection in the Con-
trol B register is set to one of four arbitrary wave-
form modes (See the Transmitter section). The
arbitrary pulse shape of mark (a transmitted "1") is
specified by describing the pulse shape across three
Unit Intervals (UIs). One UI in DS1 applications is
648 ns (1.544 MHz period) and one UI in E1 appli-
cations is 488 ns (2.048 MHz period). For example,
arbitrary waveform generation allows the DSX-1
return-to-zero "tail" to extend further into the next
UI or allows T1 long-haul waveforms to be defined
across all three UIs. The amplitude of a space (a
transmitted "0") is fixed at zero volts.
28
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
LSB
MSB
LSB
Description
Description
Serial Port Address: 0x18; Parallel Port Address: 0xY8
Serial Port Address: 0x19; Parallel Port Address: 0xY9
0
0
Arbitrary Waveform Register (Channel 1)
Arbitrary Waveform Register (Channel 2)
Table 9. Arbitrary Waveform Registers
1
1
DS261PP5
Arbitrary pulse shape definitions
Arbitrary pulse shape definitions
All three UIs are divided into 14 equal phases for a
total of 42 phase segments. The shape of the pulse
is then defined by writing the amplitude of each
phase segment to the Arbitrary Waveform register
42 times in sequence from UI1/phase1 to
UI3/phase14. The custom pulse shape must be de-
fined using the Arbitrary Waveform register before
setting the CON[3:0] configuration selection to one
of the arbitrary generation settings (i.e., 1001,
1010, or 1011).
For DS1 applications, the CS61584A divides the
648 ns UI into 14 equal phases of 46.3 ns. For
DSX-1 applications, the 648 ns UI is divided into
13 equal phases of 49.8 ns. The phase amplitude in-
formation written for phase 14 of each UI is ig-
nored. For E1 applications, the 488 ns UI is divided
into 12 equal phases of 40.7 ns. The phase ampli-
Definition
Definition
0
0
CS61584A
CS61584A
DS261PP5
undefined
undefined
DS261F1
Reset
Reset
Value
Value