CS61584A-IL3 Cirrus Logic Inc, CS61584A-IL3 Datasheet - Page 32

• Manufacturer Part Number: CS61584A-IL3
• Description: Network Controller & Processor ICs IC 3.3V/5V Dul T1/E1 Line Intrfc Unit
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IL3

• Product: Framer
• Number Of Transceivers: 2
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 3.465 V, 5.25 V
• Supply Voltage (min): 3.135 V, 4.75 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32
10.1 JTAG Data Registers (DR)
The test data registers are the Boundary-Scan Reg-
ister (BSR), the Device Identification Register
(DIR), and the Bypass Register (BR).
Boundary Scan Register: The BSR is connected in
parallel to all the digital I/O pins, and provides the
mechanism for applying/reading test patterns
to/from the board traces. The BSR is 62 bits long
and is initialized and read using the instruction
SAMPLE/PRELOAD. The bit ordering for the
BSR is the same as the top-view package pin out,
beginning with the LOS1 pin and moving counter-
clockwise to end with the PD1 pin as shown in Ta-
ble 10. Note that the analog, oscillator, power,
ground, CLKE/IPOL, and MODE pins are not in-
cluded as part of the boundary-scan register.
The input pins require one bit in the BSR and only
one J-TCK cycle is required to load test data for
each input pin.
The output pins have two bits in the BSR to define
output high, output low, or high impedance. The
first bit (shifted in first) selects between an output-
enabled state (bit set to 1) or high-impedance state
(bit set to 0). The second bit shifted in contains the
test data that may be output on the pin. Therefore,
two J-TCK cycles are required to load test data for
each output pin.
The bi-directional pins have three bits in the BSR
to define input, output high, output low, or high im-
pedance. The first bit shifted into the BSR config-
ures the output driver as high-impedance (bit set to
0) or active (bit set to 1). The second bit shifted into
the BSR sets the output value when the first bit is 1.
The third bit captures the value of the pin. This pin
may have its value set externally as an input (if the
first bit is 0) or set internally as an output (if the
first bit is 1). To configure a pad as an input, the J-
TDI pattern is 0X0. To configure a pad as an out-
put, the J-TDI pattern is 1X1. Therefore, three J-
TCK cycles are required to load test data for each
bi-directional pin.
32
DS261PP5
When JTAG testing is conducted in Host mode, the
polarity of the INT pin is determined by the state of
the IPOL pin. The JTAG BSR should configure the
INT pin as an input in Hardware mode and as an
output in Host mode.
Device Identification Register: The DIR provides
the manufacturer, part number, and version of the
CS61584A. This information can be used to verify
that the proper version or revision number has been
used in the system under test. The DIR is 32 bits
long and is partitioned as shown in Table 11. Data
from the DIR is shifted out to J-TDO LSB first.
BSR Bits
12 - 13
15 - 17
19 - 21
22 - 24
25 - 27
28 - 30
31 - 33
34 - 36
37 - 39
40 - 42
45 - 46
47 - 48
49 - 50
53 - 55
56 - 58
10 - 11
0 - 2
3 - 5
8 - 9
14
18
43
44
51
52
59
60
61
6
7
Table 10. Boundary Scan Register
RLOOP2, SCLK, RD(DS)
TAOS2, SPOL, AD2
LLOOP, SDO, AD0
CON31, WR(R/W)
TAOS1, SDI, AD1
RPOS1, RDATA1
CON22, ALE(AS)
RPOS2, RDATA2
TPOS1, TDATA1
TPOS2, TDATA2
RNEG1, BPV1
RNEG2, BPV2
RLOOP1, INT
TNEG1, AIS1
TNEG2, AIS2
CON01, AD3
CON02, AD4
CON12, AD6
CON21, AD7
CON32, BTS
LOS1, SAD6
ATTEN1, CS
CON11, AD5
LOS2, SAD7
PD2, SAD5
PD1, SAD4
Pin Name
RCLK1
RCLK2
TCLK1
TCLK2
CS61584A
CS61584A
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
bi-directional
Pad Type
DS261PP5
output
output
output
output
output
output
input
input
input
input
input
input
input
input
input
input
input
DS261F1