CS61577-IL1R Cirrus Logic Inc, CS61577-IL1R Datasheet - Page 20

• Manufacturer Part Number: CS61577-IL1R
• Description: Network Controller & Processor ICs IC T1/E1 Low PWR Line Interface Unit
• Manufacturer: Cirrus Logic Inc

Specifications of CS61577-IL1R

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Supplies
RGND - Ground, Pin 22.
RV+ - Power Supply, Pin 21.
TGND - Ground, Transmit Driver, Pin 14.
TV+ - Power Supply, Transmit Driver, Pin 15.
Oscillator
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
Control
ACLKI - Alternate External Clock Input, Pin 1.
CLKE - Clock Edge, Pin 28. (Host Mode)
CS - Chip Select, Pin 26. (Host Mode)
INT - Receive Alarm Interrupt, Pin 23. (Host Mode)
Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.
Power supply for all subcircuits except the transmit driver; typically +5 Volts.
Power supply ground for the transmit driver; typically 0 Volts.
Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than
0.3 V.
A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or
2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying
XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10.
Overdriving the oscillator with an external clock is not supported.
A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground.
During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator.
Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and
SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS
and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of
SCLK.
This pin must transition from high to low to read or write the serial port.
Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing
"clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the
power supply through a resistor.