COM20019I-HT SMSC, COM20019I-HT Datasheet
COM20019I-HT
Specifications of COM20019I-HT
Related parts for COM20019I-HT
COM20019I-HT Summary of contents
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... Sequential Access to Internal RAM Software Programmable Node ID COM20019I 3VLJP for 28 pin PLCC * package COM20019I 3V-DZD for 28 pin PLCC * Lead-Free RoHS Compliant package COM20019I 3V-HT for 48 pin TQFP Lead-Free RoHS Compliant package * TQFP package is recommended for new design SMSC COM20019I 3.3V Rev.C COM20019I 3 ...
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... OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 2 DATASHEET SMSC COM20019I 3.3V Rev.C ...
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... Access Speed.........................................................................................................................................37 6.4 SOFTWARE INTERFACE .............................................................................................................37 6.4.1 Selecting RAM Page Size.......................................................................................................................38 6.4.2 Transmit Sequence.................................................................................................................................39 6.4.3 Receive Sequence..................................................................................................................................40 6.5 COMMAND CHAINING.................................................................................................................. 41 6.5.1 Transmit Command Chaining .................................................................................................................42 6.5.2 Receive Command Chaining ..................................................................................................................42 6.6 RESET DETAILS ........................................................................................................................... 43 SMSC COM20019I 3.3V Rev.C TABLE OF CONTENTS Page 3 DATASHEET Rev. 11-07-08 ...
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... Pin TQFP Package Outline and Parameters ............................................................................ 65 Chapter 10 Appendix A...................................................................................................................... 66 10.1 NOSYNC Bit................................................................................................................................... 66 10.2 EF Bit.............................................................................................................................................. 66 Chapter 11 Appendix B ...................................................................................................................... 69 Chapter 12 Appendix C...................................................................................................................... 70 12.1 Software Identification of the COM20019I 3V Rev B and Rev C................................................... 70 Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 4 DATASHEET SMSC COM20019I 3.3V Rev.C ...
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... Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ............................................17 Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE ...................................18 Figure 5.3 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE............................................................................19 Figure 5.4 - COM20019I 3V NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS .....................................21 Figure 5.5 - INTERNAL BLOCK DIAGRAM ..................................................................................................................23 Figure 6.1 - SEQUENTIAL ACCESS OPERATION ......................................................................................................37 Figure 6 ...
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... Using an ARCNET protocol engine is the ideal solution for embedded control applications because it provides a deterministic token-passing protocol, a highly reliable and proven networking scheme, and a data rate 312.5 Kbps when using the COM20019I 3V. A token-passing protocol provides predictable response times because each network event occurs within a predetermined time interval, based upon the number of nodes on the network ...
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... A1 2 A2/ALE 3 AD0 4 AD1 5 AD2 VSS Package: 28-Pin PLCC Packages: 24-Pin DIP or 28-Pin PLCC Ordering Information: COM20019 I P SMSC COM20019I 3.3V Rev.C Pin Configurations 24 VDD 23 nRD/nDS 25 22 nWR/DIR nWR/DIR 26 21 nCS 27 nRD/nDS 20 nINTR VDD 28 19 nRESET IN COM20019I 3V 18 nTXEN 1 A0/nMUX 17 RXIN ...
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... D3 7 VDD VSS Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM COM20020I 48 PIN TQFP NOTE: BUSTMG pin is only TQFP package Page 8 DATASHEET 36 nCS 35 VDD 34 nINTR 33 N/C 32 VDD 31 nRESET 30 VSS 29 nTXEN 28 RXIN 27 N/C 26 BUSTMG 25 nPULSE2 SMSC COM20019I 3.3V Rev.C ...
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... Select - 26 Read/Write Bus Timing Select SMSC COM20019I 3.3V Rev.C Description of Pin Functions SYMBOL I/O MICROCONTROLLER INTERFACE On a non-multiplexed mode, A0-A2 are address A0/nMUX IN input bits. (A0 is the LSB multiplexed A1 IN address/data bus, nMUX tied Low left open, and ALE is tied to the Address Latch Enable signal ...
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... Oscillation frequency range is from 10 MHz to XTAL2 OUT 20 MHz external TTL clock is used instead, it must be connected to XTAL1 with a 390ohm pull-up resistor, and XTAL2 should be left floating. +3.3 Volt power supply pins. VDD PWR Ground pins. VSS PWR Non-connection N/C Page 10 DATASHEET DESCRIPTION SMSC COM20019I 3.3V Rev.C ...
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... NAK Y RI? ACK Transmit Free Buffer Enquiry No Y Activity for 597 ACK Set TA NAK? 1 Pass the Token Figure 3.1 - COM20019I 3V OPERATION No Increment Y N Activity NID for 597.6 us? SEND ACK Page 11 DATASHEET SOH? N Write SID No Activity to Buffer for 656 uS? Y DID ...
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... A significant advantage of the COM20019I 3V is its ability to adapt to changes on the network. Whenever a new node is activated or deactivated, a NETWORK RECONFIGURATION is performed. When a new COM20019I 3V is turned on (creating a new active node on the network the COM20019I 3V has not received an INVITATION TO TRANSMIT for 6.72S software reset occurs, the COM20019I 3V causes a NETWORK RECONFIGURATION by sending a RECONFIGURE BURST consisting of eight marks and one space repeated 765 times ...
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... S timeout expires, the COM20019I 3V releases control of the line. RECONFIGURATION, INVITATIONS TO TRANSMIT are sent to all NIDs (1-255). Each COM20019I 3V on the network will finally have saved a NID value equal to the ID of the COM20019I 3V that it released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK RECONFIGURATION occurs ...
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... During NETWORK RECONFIGURATION, activity will appear on the line every 656 μS. This 656 μS is equal to the Response Time of 597.6 μS plus the time it takes the COM20019I 3V to start retransmitting another message (usually another INVITATION TO TRANSMIT). 4.5.3 Reconfiguration Time If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK RECONFIGURATION ...
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... An ACK (ACKnowledgement--ASCII code 86H) character 4.6.5 Negative Acknowledgements A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character SMSC COM20019I 3.3V Rev.C DID DID COUNT data ALERT BURST ACK ...
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... Since microcontrollers do not typically have READY inputs, standard peripherals cannot extend cycles to extend the access time. The access time of the COM20019I 3V, on the other hand fast that it does not need to limit the speed of the microcontroller. The COM20019I 3V is designed to be flexible so that it is independent of the microcontroller speed ...
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... A15 RESET nRD nWR nINT1 8051 RXIN TXEN nPULSE1 nPULSE2 GND BACKPLANE CONFIGURATION FIGURE A Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE SMSC COM20019I 3.3V Rev.C COM20022 AD0-AD2, D3-D7 A2/BALE RXIN nCS 75176B or nRESET nTXEN Equiv. nPULSE1 nRD/nDS nPULSE2 nWR/DIR ...
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... HYC9088 RXIN 12 N/C 11 5.6K nPULSE1 1/2W 5.6K nPULSE2 1/2W 17, 19 Traditional Hybrid 0.47 Configuration uF - *Valid for 2.5 Mbps only. uF FIGURE C Page 18 DATASHEET 75176B or Equiv. Differential Driver Configuration * Media Interface may be replaced with Figure 0.01 uF 1KV SMSC COM20019I 3.3V Rev.C ...
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... High Speed CPU Bus Timing Support High speed CPU bus support was added to the COM20019I 3V. The reasoning behind this is as follows: With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to these timings ...
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... Normal Speed CPU Read and Write High Speed CPU Read and Normal Speed CPU Write BUS TIMING MODE X High Speed CPU Read and Write 0 Normal Speed CPU Read and Write 1 High Speed CPU Read and Normal Speed CPU Write Page 20 DATASHEET SMSC COM20019I 3.3V Rev.C ...
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... It issues a 1.6µS negative pulse to transmit a logic "1". Note that when used in the open-drain mode, the COM20019I 3V does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up resistor. This pull-up should not take the place of the resistor required on the media for open drain mode ...
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... The nPULSE1 signal issues a 1.6µS negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20019I 3V is disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive. ...
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... ADDRESS DECODING CIRCUITRY AD0-AD2, D3-D7 STATUS/ nINTR COMMAND REGISTER RESET nRESET LOGIC nRD/nDS nWR/DIR BUS ARBITRATION nCS CIRCUITRY Figure 5.5 SMSC COM20019I 3. RAM MICRO- SEQUENCER AND WORKING REGISTERS OSCILLATOR NODE ID RECONFIGURATION LOGIC TIMER - INTERNAL BLOCK DIAGRAM Page 23 DATASHEET ADDITIONAL REGISTERS nPULSE1 ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Table 5.1 - Typical Media NOMINAL ATTENUATION PER 1000 FT. IMPEDANCE 93Ω 75Ω 75Ω 150Ω 100Ω 105Ω Page 24 DATASHEET AT 5 MHZ 5.5dB 7.0dB 5.5dB 7.0dB 17.9dB 16.0dB SMSC COM20019I 3.3V Rev.C ...
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... The COM20019I 3V derives a 625 kHz and a 312.5 kHz clock from the output clock of the Clock Multiplier. These clocks provide the rate at which the instructions are executed within the COM20019I 3V. The 625 kHz clock is the rate at which the program counter operates, while the 312 ...
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... Interrupt Mask Register (IMR) The COM20019I 3V is capable of generating an interrupt signal when certain status bits become true. A write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic " ...
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... Node ID. Refer to the Initialization Sequence section for further detail on the use of the DUPID bit. The core of the COM20019I 3V does not wake up until a Node ID other than zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node, and no reconfigurations are caused by this node ...
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... SUBAD0 and SUBAD1 point to the selection in Register 7. 6.2.11 Sub-Address Register The sub-address register is new to the COM20019I 3V, previously a reserved register. Bits 2, 1 and 0 are used to select one of the registers assigned to address 7h. SUBAD1 and SUBAD0 already exist in the Configuration register on the COM20020B. They are exactly same as those in the Sub-Address register. If the SUBAD1 and SUBAD0 bits in the Configuration register are changed, the SUBAD1and SUBAD0 in the Sub-Address register are also changed ...
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... High Speed CPU bus support. The EF bit is used to enable the new timing for certain functions in the COM20019I 3V ( the timing is the same as in the COM20020 Rev. B). See Appendix “A”. The NOSYNC bit is used to enable the NOSYNC function during initialization. If this bit is reset, the line has to be idle for the RAM initialization sequence to be written. If set, the line does not have to be idle for the initialization sequence to be written. See Appendix “ ...
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... Enquiry. This bit is cleared upon the "POR Clear Flags" command. Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. Refer to the Improved Diagnostics section for further detail. Page 30 DATASHEET SMSC COM20019I 3.3V Rev.C ...
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... Available) status bit to logic "1" when the COM20019I 3V next receives the token. This command will cancel any pending receive command. If the COM20019I 3V is not yet receiving a packet, the RI (Receiver Inhibited) bit will be set to logic "1" the next time the token is received. If packet reception is already underway, reception will run to its normal conclusion ...
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... If "c" logic "0", the device handles only short packets. This command resets certain status bits of the COM20019I 3V. A logic "1" on "p" resets the POR status bit and the EXCNAK Diagnostic status bit. A logic "1" on "r" resets the RECON status bit ...
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... Table 6.9 - Configuration Register SYMBOL DESCRIPTION RESET A software reset of the COM20019I 3V is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Status Register, the Next ID Register, and the Diagnostic Status Register. This bit must be brought back to logic " ...
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... Note that ACKs are only sent for packets received with a destination ID equal to the COM20019I 3V's programmed node ID. This feature can be used to put the COM20019I 'listen-only' mode, where the transmitter is disabled and the COM20019I 3V is not passing tokens. ...
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... These bits are undefined. They must This bit is used to enable the new enhanced functions in the COM20019I 3V Disable (Default Enable the timing and function is the same as in the COM20020, Revision B. See appendix “A”. EF bit must be ‘1’ if the data rate is over 5Mbps. ...
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... I/O Address 04H D0-D7 Address Pointer Register I/O Address 02H High 11-Bit Counter Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Memory Data Bus 8 I/O Address 03H Low Memory Address Bus 11 Page 36 DATASHEET INTERNAL RAM SMSC COM20019I 3.3V Rev.C ...
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... INTERNAL RAM The integration of the RAM in the COM20019I 3V represents significant real estate savings. The most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control functions which were necessary to interface to the RAM ...
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... Please note that it is the responsibility of software to reserve 512 bytes for each receive page if the device is configured to handle long packets. The COM20019I 3V does not check page boundaries during reception. If the device is configured to handle only short packets, then both transmit and receive pages may be allocated as 256 bytes long, freeing at least 1KByte at any given time ...
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... The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM20019I 3V puts the local ID in this location, therefore it is not necessary to write into this location. Please note that a short packet may contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes ...
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... These situations can be determined by either using the improved diagnostic features of the COM20019I 3V or using another software timeout which is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length message. ...
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... RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the COM20019I 3V sets the RI bit to logic "1" to signal the microcontroller that the reception is complete. ...
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... The COM20019I 3V guarantees a minimum of 200nS (at EF=1) interrupt inactive time interval between interrupts. The TMA bit is also double buffered to reflect whether the appropriate transmission was a success. The TMA bit should only be considered valid after the corresponding TTA bit has been set to a logic " ...
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... Setup1 Register should be written before the Node ID Register. Once the Node ID Register is written to, the COM20019I 3V reads the value and executes two write cycles to the RAM buffer. Address 0 is written with the data D1H and address 1 is written with the Node ID. The data pattern D1H was chosen arbitrarily, and is meant to provide assurance of proper microsequencer operation ...
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... Tentative ID. To determine the next logical node, the software should read the Next ID Register. 6.8 IMPROVED DIAGNOSTICS The COM20019I 3V allows the user to better manage the operation of the network through the use of the internal Diagnostic Status Register. A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this node expired, causing a reconfiguration by this node ...
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... NODE ID already exists on the network. The software should periodically place values in the Tentative ID Register and monitor the New Next ID bit to maintain an updated network map. 6.9 OSCILLATOR The COM20019I 3V contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms an oscillator. SMSC COM20019I 3.3V Page 45 DATASHEET Rev ...
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... If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external resistor is required, since the COM20019I 3V contains an internal resistor. The crystal must have an accuracy of 0.020% or better. The oscillation frequency range is from 10 MHz to 20 MHz. The crystal must have an accuracy of 0.010% or better when the internal clock multiplier is turned on. The oscillation frequency must be 20MHz when the internal clock multiplier is turned on ...
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... Low Input Voltage 1 (All inputs except XTAL1) High Input Voltage 1 (All inputs except XTAL1) Low Input Voltage 2 (XTAL1) High Input Voltage 2 (XTAL1) Low Output Voltage 1 (nTXEN) High Output Voltage 1 (nTXEN) SMSC COM20019I 3.3V Operational Description SYMBOL MIN TYP MAX 0.8 V -0.3 IL1 V 2.0 5 ...
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... Page 48 DATASHEET UNIT COMMENT V I =8mA SINK V I =-4mA SOURCE V I =8mA SINK Open Drain Driver mA 312.5 Kbps All Outputs Open µA V =0.0V IN µA V < V < UNIT COMMENT pF pF Maximum Capacitive Load which can be supported by each output. SMSC COM20019I 3.3V Rev.C ...
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... Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin. Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". SMSC COM20019I 3.3V t 2.0V 0.8V 2.0V 50% 0.8V t Figure 7 MEASUREMENTS ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Timing Diagrams VALID DATA VALID t1 t2 t12 t11 t6 t13 t5 t9 MUST BE: RBUSTMG bit = 0 Parameter 4T if SLOW ARB = 0 opr if SLOW ARB = 1 from the trailing edge of nDS to ARB Page 50 DATASHEET t7 t14 Note 2 t8 t10 min max units ARB SMSC COM20019I 3.3V Rev.C ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I 3.3V VALID DATA VALID t1 t2 ...
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... VALID DATA VALID t1 t2 t12 t5 t6 t13 t9 Parameter min Next )** * 4T ARB SLOW ARB = 0 opr from the trailing edge of nDS to the leading edge of the ARB from the trailing edge of nDS to ARB Page 52 DATASHEET t7 Note 2 t8** t8 t14 t10 max units SMSC COM20019I 3.3V Rev.C ...
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... Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE SMSC COM20019I 3.3V VALID VALID DATA t1 t2, t4 ...
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... VALID DATA CASE 1: RBUSTMG bit = 0 min Parameter 4T to nRD Low if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 54 DATASHEET Note 2 t7 max units 5 ARB nS 40 SMSC COM20019I 3.3V Rev.C ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I 3.3V VALID t1 t3 Note 3 t5 ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 CASE 1: RBUSTMG bit = 0 Parameter if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nDS to ARB Page 56 DATASHEET t11 Note 2 t9 VALID DATA min max units 5 ARB SMSC COM20019I 3.3V Rev.C ...
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... COM20019 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I 3.3V VALID t10 ...
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... VALID DATA min Next )** 4T ARB 30*** SLOW ARB = 0 opr from the trailing edge of nWR to the leading edge ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 58 DATASHEET Note 2 t5** t7 max units SMSC COM20019I 3.3V Rev.C ...
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... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 8.10 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE SMSC COM20019I 3.3V VALID t10 t6 ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t3 t5 t10 t8 VALID DATA min Next Time )** * 4T ARB 10 30*** from the trailing edge of nDS to the leading edge ARB from the trailing edge of nDS to ARB Page 60 DATASHEET t11 Note 2 t6 max units SMSC COM20019I 3.3V Rev.C ...
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... Any cycle occurring after a write to the Address Pointer Low Register requires a minimum the next nDS. Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.11 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE SMSC COM20019I 3.3V VALID t10 t8 ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM t10 t12 t11 Parameter Page 62 DATASHEET t13 t8 LAST BIT (3200 nS BIT TIME) min typ max units - 1600* nS 3200 800* nS 800* nS 1600 -25 5500 5700 nS 3900 4100 nS 10 1600* nS 3200 SMSC COM20019I 3.3V Rev.C ...
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... High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 312.5 Kbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD Figure 8.15 - RESET AND INTERRUPT TIMING SMSC COM20019I 3.3V t2 1.0V min -200 t2 min ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Package Outlines PIN 28L .160-.180 A .090-.120 .013-.021 .026-.032 B 1 .020-.045 C D .485-.495 .450-.456 .390-.430 D 3 .300 .050 BSC F .042-.056 G .042-.048 J .000-.020 R .025-.045 Page 64 DATASHEET SMSC COM20019I 3.3V Rev.C ...
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... E1 6.90 H 0. 0.50 Basic θ 0.17 R1 0.08 R2 0.08 ccc ~ ccc ~ Note 1: Controlling Unit: millimeter SMSC COM20019I 3.3V MAX ~ 1.6 0.10 0.15 1.40 1.45 9.00 9.20 1 4.50 4. Span Measure from Centerline 2 7.00 7.10 9.00 9.10 1 4.50 4. Span Measure from Centerline 2 7 ...
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... RAM initialization sequence to be written. The following discussion describes the function of this bit: During initialization, after the CPU writes the Node ID, the COM20019I 3V will write "D1"h data to Address 000h and Node-ID to Address 001h of its internal RAM within 96uS. These values are read as part of the diagnostic test ...
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... CKP3-1 with Pre-Scalar’s internal clocks. C) Shorten The Write Interval Time To The Command Register The COM20019I 3V limits the write interval time for continuous writing to the Command register. The minimum interval time is changed by the Data Rate. It's 800 nS at the 312.5 Kbps and 1.6 μ the 156.25 Kbps. This 1.6 μ ...
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... Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which results in an incorrect network map. It can be avoided by a carefully coded software routine, but this requires the programmer to have deep knowledge of how the COM20019I 3V works. Duplicate-ID is mainly used for generating the Network MAP. This has the same issue as Tentative-ID. ...
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... SA15-SA4 P 12 SD7-SD0 A 8 nIOR nIOW SA2-SA0 3 IRQm nIOCS16 DRQn nDACK TC nREFRESH RESETDRV Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS SMSC COM20019I 3.3V LS688x2 12 bit Comparators Q I/O Address Seeting (DIP Switches) P=Q 12 LS245 A 16 bit Bus Transceivers DIR 3 Schmitt-Trigger Buffer ...
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... Chapter 12 Appendix C 12.1 Software Identification of the COM20019I 3V Rev B and Rev C In order to properly write software to work with the COM20019I 3V Rev B and necessary to be able to identify the different revisions of the part. To identify the COM20019I 3V Revision follow the following procedure: 1. Write 0x00 to Register-5 2 ...