Si3016-KS Silicon Laboratories Inc, Si3016-KS Datasheet - Page 30

Telecom Line Management ICs Line-Side device for processors

Si3016-KS

Manufacturer Part Number
Si3016-KS
Description
Telecom Line Management ICs Line-Side device for processors
Manufacturer
Silicon Laboratories Inc
Type
Chipsetr
Datasheet

Specifications of Si3016-KS

Product
Modem Module
Interface Type
Wire
Supply Current
0.3 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
SOIC-16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3016-KS
Manufacturer:
SI
Quantity:
20 000
Part Number:
Si3016-KSR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si3016
Register 6. DAA Control 2
Reset settings = 0111_0000
Register 7. Reserved
30
Bit
6,1
5,0
Bit
7:0
7
4
3
2
Name
Name
Type
Type
Bit
Bit
Reserved Read returns zero.
Reserved Read returns zero.
Reserved Read returns zero.
ARM[1:0]
ATM[1:0]
Name
Name
PDN
PDL
D7
D7
AOUT Transmit Path Level Control.
00 = –26 dB transmit path attenuation for call progress AOUT pin only.
01 = –20 dB transmit path attenuation for call progress AOUT pin only.
10 = Mutes transmit path for call progress AOUT pin only.
11 = –32 dB transmit path attenuation for call progress AOUT pin only.
AOUT Receive Path Level Control.
00 = –6 dB receive path attenuation for call progress AOUT pin only.
01 = 0 dB receive path attenuation for call progress AOUT pin only.
10 = Mutes receive path for call progress AOUT pin only.
11 = –12 dB receive path attenuation for call progress AOUT pin only.
Powerdown Line-Side Chip.
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the Si3016 in lower power mode.
Powerdown.
0 = Normal operation.
1 = Powers down the system-side module. An internal RESET to the system-side module is
required to restore normal operation.
ATM[1]
R/W
D6
D6
ARM[1]
R/W
D5
D5
Rev. 1.0
PDL
R/W
D4
D4
Function
Function
PDN
R/W
D3
D3
D2
D2
ATM[0]
R/W
D1
D1
ARM[0]
R/W
D0
D0

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