LX256EB-35FN484C Lattice, LX256EB-35FN484C Datasheet - Page 58
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LX256EB-35FN484C
Manufacturer Part Number
LX256EB-35FN484C
Description
Analog & Digital Crosspoint ICs E-Series, 256 I/O Switch Matrix, 2.5V, 3.5ns, Pb-Free
Manufacturer
Lattice
Datasheet
1.LX256EV-5FN484C.pdf
(75 pages)
Specifications of LX256EB-35FN484C
Maximum Dual Supply Voltage
2.7 V
Minimum Dual Supply Voltage
2.3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
2.5 V
Supply Type
Triple
Configuration
256 x 256
Package / Case
FPBGA-484
Data Rate
38 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
ispGDX2-64 Logic Signal Connections (Continued)
GND
BK7_IO6
BK7_IO7/PLL_LOCK2
GOE1
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.
5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for channel 1A.
transmit data (TXD) is present in the cell, the associated pin is available for input only.
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associated pins through the output MUX and
the pins.
able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for
transmitter.
Signal Name
sysIO
Bank
7
7
7
7
Pair/Polarity
LVDS
31N
31P
-
-
Block
GDX
1B
1B
-
-
MRB
14
15
-
-
HSI1B_CDRRSTb
SERDES Mode
55
I/O Pin
-
-
-
1
SERDES Mode
I/O Cell
-
-
-
-
ispGDX2 Family Data Sheet
2
FIFO3_FIFORSTb
FIFO Mode I/O
FIFO3_FULL
Cell/Pin
-
-
3
fpBGA
GND
100
K5
H5
J5