LAN9115-MD SMSC, LAN9115-MD Datasheet - Page 126
LAN9115-MD
Manufacturer Part Number
LAN9115-MD
Description
Ethernet ICs Efficient Sngl Chip 10/100 Ethrnt
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet
1.LAN9115-MT.pdf
(136 pages)
Specifications of LAN9115-MD
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
1.8 V
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Revision 1.5 (07-11-08)
6.7
FIFO_SEL
nCS, nWR
Data Bus
SYMBOL
A[2:1]
t
cycle
t
t
t
t
t
t
asu
dsu
csh
csl
ah
dh
In this mode the upper address inputs are not decoded, and any write to the LAN9115 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9115. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note: The “Data Bus” width is 16 bits
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
TX Data FIFO Direct PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Table 6.8 TX Data FIFO Direct PIO Write Timing
DATASHEET
126
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
165
32
13
0
0
7
0
TYP
MAX
SMSC LAN9115
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns
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