TMC2074-NE SMSC, TMC2074-NE Datasheet - Page 56

• Manufacturer Part Number: TMC2074-NE
• Description: Network Controller & Processor ICs Standalone Mode CircLink Cntlr
• Manufacturer: SMSC

Specifications of TMC2074-NE

• Product: Controller Area Network (CAN)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.12.2 Time-synchronous Sequence
Supplement:
Revision 0.2 (10-23-08)
NST carry output
The change of any digit in NST can be output as a periodic pulse to the nNSTCOUT pin. NSTC [3:0] in the
CARRY register (external pin in the standalone mode) is used to select the digit. The pulse width of the
carry output is the same length as one cycle of the NST resolution. As long as NST is synchronized
properly, every node can output the pulse with the same phase.
Time readout
Accessing the NST register can dynamically provide the latest time data. Since NST is a 16 bit wide
counter, it is necessary to read the even address side (10h) first when an 8-bit bus is used. When the even
address is read out, the remaining 8 bits of the NST are latched internally
CM and CS nodes
To synchronize NST, one clock master (CM) should be designated on the network. The other nodes
become clock slave nodes (CS node). The clock master ID (CMID) must be set in the CMID register on
every node (external pins in the standalone mode). All nodes on the network use the same value as CMID.
CM node:
CMID equals to its node ID
Only one node on the network
Counts NST and notifies the CS nodes of the NST by sending packets.
CS node:
CMID not equal to its node ID
Receives a packet from the node specified by CMID and synchronizes NST with its own clock.
Preset at first receive
The NST counter of each node starts free running immediately after power-up. CS nodes preset the
received NST as the NST of its own after receiving the first packet from the CM node. This preset
operation is performed only once for the first receive.
The preset operation is performed after power-up and also immediately after resetting NSTSTOP in the
MODE register from 1 to 0, after writing CMID register, and after software reset.
Phase tracking after second receive
The CS nodes that are preset by the first reception from the CM node switch into the time synchronization
mode by PLL.
The CS nodes that switch into PLL operation keep comparing their NST to the received NST at every
receive from the CM node. If the phase is different, the CS nodes dynamically control the speed of their
counters to adjust phase to correspond to the phase of the NST in the CM node.
When the difference count value between the receiver’s NST and the received NST from CM node,
is +2 and above, the receiver’s counter is slowed to compensate. When the difference is –1 and
DATASHEET
Page 56
Dual Mode CircLink™ Controller
SMSC TMC2074
Datasheet