DV3100 DIGIVIEW, DV3100 Datasheet - Page 117

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DV3100

Manufacturer Part Number
DV3100
Description
LOGIC ANALYSER, DIGITAL, 100MHZ, 18CH
Manufacturer
DIGIVIEW
Datasheet

Specifications of DV3100

No. Of Data Channels
18
No. Of Clock Inputs
8
Frequency
100MHz
Power Consumption
2.5W
External Height
0.75"
External Width
2.8"
External Depth
4.75"
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Trigger Match Circuits
Match Duration
Trigger Pass Count
Trigger Output Sources
External Trigger Output
Threshold Circuits
Threshold Range
Threshold Accuracy
Maximum voltage
(Continuous, all
channels)
Impedance
DV1-100
Configuration:
AND Pattern detect)
>100KOhm // <10pf
(18 bit AND:
(18 bit OR: rising,
Edge detect
Pattern
Edge detect
OR Pattern detect
OR (Edge detect
falling, either)
0, 1, X)
>1KOhm // <10pf
2 Standard
+- 100mv
(<0, >5V)
+10/-5V
(0-5V)
(1.6V)
Fixed
No
No
No
1
DV3100
Each can be
configured as:
- 1 per match circuit
- up to 1M samples
each
input products of all 8
match circuits)
Yes (up to 1 Million per
(18 bit OR: rising,
(18 bit AND:
Edge Detect
Patterns
Stable (18 bit)
> (18 bit RANGE)
>= (18 bit RANGE)
< (18 bit RANGE)
<= (18 bit RANGE)
= (18 bit RANGE)
<> (18 bit RANGE)
Seq 1
OR Seq 2
OR Seq 3
OR Seq4
OR (8 input sum-of-8
>50KOhm // <10pf
falling, either)
0, 1, X)
Sequencer stage)
>5KOhm // <10pf
(0.5V to 2.8V)
8 Universal
Adjustable
(<0, >3.3V)
+-20 Volts
+- 250mv
(0-3.3V)
Yes
No
1
DV3400
Each can be
configured as:
- 1 per match circuit
- up to 1M samples
each
input products of all 8
match circuits)
Yes (up to 1 Million per
(1 for for each group of
Appendicies
(36 bit OR: rising,
falling, either)
(36 bit AND:
Edge Detect
Patterns
Stable (36 bit)
> (36 bit RANGE)
>= (36 bit RANGE)
< (36 bit RANGE)
<= (36 bit RANGE)
= (36 bit RANGE)
<> (36 bit RANGE)
Seq 1
OR Seq 2
OR Seq 3
OR Seq4
OR (8 input sum-of-8
0, 1, X)
Sequencer stage)
50KOhms // < 3pf
(BNC connector)
18 channels)
(-6V to +6V)
8 Universal
Adjustable
+-50 Volts
+- 250mv
Yes,
Yes
2
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