HEF4526BTD-T NXP Semiconductors, HEF4526BTD-T Datasheet - Page 2
![Counter ICs PROGRMMABL 4-BIT BCD DOWN CTR](/photos/15/59/155965/soic16_sml.jpg)
HEF4526BTD-T
Manufacturer Part Number
HEF4526BTD-T
Description
Counter ICs PROGRMMABL 4-BIT BCD DOWN CTR
Manufacturer
NXP Semiconductors
Datasheet
1.HEF4526BP652.pdf
(10 pages)
Specifications of HEF4526BTD-T
Counter Type
Binary Counters
Mounting Style
SMD/SMT
Package / Case
SOT-109
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
HEF4526BT,653
Philips Semiconductors
DESCRIPTION
The HEF4526B is a synchronous programmable 4-bit
binary down counter with an active HIGH and an active
LOW clock input (CP
load input (PL), four parallel inputs (P
feedback input (CF), four buffered parallel outputs (O
O
asynchronous master reset input (MR).
This device is a programmable, cascadable down counter
with a decoded TC output for divide-by-n applications. In
single stage applications the TC output is connected to PL.
CF allows cascade divide-by-n operation with no
additional gates required.
FAMILY DATA, I
See Family Specifications
January 1995
3
Programmable 4-bit binary down counter
), a terminal count output (TC) and an overriding
DD
LIMITS category MSI
0
, CP
1
), an asynchronous parallel
0
to P
3
), a cascade
Fig.1 Functional diagram.
0
to
2
Information on P
is HIGH, independent of all other input conditions except
MR, which must be LOW. When PL and CP
counter advances on a LOW to HIGH transition of CP
When PL is LOW and CP
on a HIGH to LOW transition of CP
counter is in the zero state (O
and CF is HIGH and PL is LOW. A HIGH on MR resets the
counter (O
conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
0
to O
0
3
to P
= LOW) independent of other input
3
is loaded into the counter while PL
0
is HIGH, the counter advances
0
= O
1
Product specification
1
. TC is HIGH when the
= O
HEF4526B
2
= O
1
are LOW, the
3
= LOW)
MSI
0
.