FQD18N20V2TM Fairchild Semiconductor, FQD18N20V2TM Datasheet - Page 5

• Manufacturer Part Number: FQD18N20V2TM
• Description: MOSFET N-CH 200V 15A DPAK
• Manufacturer: Fairchild Semiconductor
• Series: QFET™r
• Type: Power MOSFETr

Specifications of FQD18N20V2TM

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 140 mOhm @ 7.5A, 10V
• Drain To Source Voltage (vdss): 200V
• Current - Continuous Drain (id) @ 25° C: 15A
• Vgs(th) (max) @ Id: 5V @ 250µA
• Gate Charge (qg) @ Vgs: 26nC @ 10V
• Input Capacitance (ciss) @ Vds: 1080pF @ 25V
• Power - Max: 2.5W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.14 Ohm @ 10 V
• Forward Transconductance Gfs (max / Min): 11 S
• Drain-source Breakdown Voltage: 200 V
• Gate-source Breakdown Voltage: +/- 30 V
• Continuous Drain Current: 15 A
• Power Dissipation: 2500 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Number Of Elements: 1
• Polarity: N
• Channel Mode: Enhancement
• Drain-source On-res: 0.14Ohm
• Drain-source On-volt: 200V
• Gate-source Voltage (max): ±30V
• Output Power (max): Not RequiredW
• Frequency (max): Not RequiredMHz
• Noise Figure: Not RequireddB
• Power Gain: Not RequireddB
• Drain Efficiency: Not Required%
• Operating Temp Range: -55C to 150C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 2 +Tab
• Package Type: DPAK
• Fall Time: 62 ns
• Rise Time: 133 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2009 Fairchild Semiconductor Corporation
10V
10V
10V
10V
12V
12V
t
t
p
p
3mA
3mA
200nF
200nF
R
R
R
R
G
G
G
G
50KΩ
50KΩ
V
V
V
V
GS
GS
GS
GS
Unclamped Inductive Switching Test Circuit & Waveforms
V
V
300nF
300nF
I
I
I
V
V
DS
DS
D
D
D
DS
DS
Resistive Switching Test Circuit & Waveforms
Gate Charge Test Circuit & Waveform
DUT
DUT
DUT
DUT
Same Type
Same Type
DUT
DUT
L
L L
as DUT
as DUT
R
R
L
L
V
V
DD
DD
V
V
DD
DD
V
V
DS
DS
BV
BV
V
V
V
V
10V
10V
DSS
DSS
V
V
I
I
V
V
DD
DD
GS
GS
AS
AS
DS
DS
GS
GS
E
E
E
10%
10%
AS
AS
AS
Q
Q
90%
90%
=
=
=
gs
gs
t
t
d(on)
d(on)
----
----
----
----
1
1
1
1
2
2
2
2
t
t
on
on
L I
L I
L I
t
t
r
r
I
I
AS
AS
AS
D
D
Q
Q
(t)
(t)
t
t
2
2
2
Q
Q
p
p
g
g
gd
gd
Charge
Charge
--------------------
--------------------
BV
BV
BV
BV
DSS
DSS
DSS
DSS
t
t
- V
- V
d(off)
d(off)
t
t
DD
DD
off
off
Time
Time
t
t
f
f
Rev. B2, January 2009
V
V
DS
DS
(t)
(t)