STV5730A STMicroelectronics, STV5730A Datasheet - Page 11

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STV5730A

Manufacturer Part Number
STV5730A
Description
Multimedia Misc On-Screen Display
Manufacturer
STMicroelectronics
Type
Satellite Receiverr
Datasheet

Specifications of STV5730A

Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Package / Case
SO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FUNCTIONAL DESCRIPTION (continued)
2 - THE MICROPROCESSOR SERIAL INTERFACE
The STV5730A is down loaded by the microprocessor through a three wire serial interface : DATA, CLK,
CSN. The CLK and CSN signals are internally ORed in order to validate the transfer when the STV5730A
is chip selected only (i.e. CSN = 0). The CSN rising edge validates the internal data transfer.
2.1 - Message Formats (see Figure 2)
16-bit, 8-bit and 0-bit formats are available. The 8-bit and 0-bit message formats may be useful to speed
up the STV5730A down loading.
This 16-bit address message loads the serial interface write pointer. This address is incremented after each
data message.
This 16-bit data message writes the data at the location indicated by the write pointer.
This 8-bit data message writes the data at the location indicated by the write pointer. The 4-bit data MSB
is copied from the last previous 16-bit data message.
The 0-bit data message writes a data at the location indicated by the write pointer. The last data is used
from the previous 8-bit or 16-bit data message.
This 16-bit control message stops the 4*fsc quartz oscillator.
This 16-bit control message resets the circuit and starts the 4*fsc quartz oscillator. This message should
not be used if an external 4 x fsc clock is used instead of the quartz. It is mandatory that reset operation is
as described in paragraph 2.3.
15
15
15
15
0
0
0
0
0
0
0
0
0
0
1
1
12
12
12
12
0
1
0
1
11
11
11
11
BUF[11:8]
8
STRU[7:6]
7
7
DATA[11:0]
don’t care
don’t care
6
5
0
DATA[7:0]
4
DEPL[4:0]
0
0
0
0
0
STV5730A
CONTROL
CONTROL
ADDRESS
DATA
DATA
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