STV5730A STMicroelectronics, STV5730A Datasheet - Page 13

• Manufacturer Part Number: STV5730A
• Description: Multimedia Misc On-Screen Display
• Manufacturer: STMicroelectronics
• Type: Satellite Receiverr

Specifications of STV5730A

• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: SO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3
3 - THE LINE LOCKED PLL
The PLL frequency is 504 * f
3.1 - Mixed Mode Behavior
In mixed mode, the internal PLL is line locked to the
incoming CVBS signal. The sync is either extracted
by the STV5730A (if C7 control bit is set) or pro-
vided by the application in a composite form on the
CSYNC pin (if C7 control bit is cleared). The
STV5730A separates the vertical sync from the
composite synchronism.
The STV5730A PLL features built-in protection
mechanismsagainst missing and parasitichorizon-
tal sync pulses. These mechanisms are activated
when the loop is locked.
FUNCTIONAL DESCRIPTION (continued)
2.3 - Initialization and Down-loading Sequence
It is important that the STV5730A is correctly reset
and initialized after the circuit is powered prior to
any writing. This routine is shown in Figure 3. The
two initialization bytes (00db 1000) must procede
the reset instruction (x2) every time it is transmitted.
Next Page
Write
Set Control Registers
RESET & INITIALIZE
Set RAM Attributes
Set Row Attributes
i.e. TEXT PAGE
* Write Pointer
* Data
* etc.
* Zoom
* Color
* Control
* Position
* Mode
* 0 to 10
3000H
3000H
00dbH
1000H
STOP
H
= 7.875MHz.
The STV5730A PLL is also insensitive to the head
switching disturbing the synchronism in VTR appli-
cations (playback).
The missing pulses may be detected. The M1
mode bit enables the detection.
In addition, the BAR input pin is available to enter
a signal that forces the PLL in free-run mode. This
capability may be used for search mode in VTRs,
to improve the loop robustness against the noise
bar. The BAR input is enabled by the M0 mode bit.
3.2 - Horizontal Sync Re-insertion
This mechanism is of interest in mixed mode, to
cancel the text horizontaljitter when the sync signal
is too bad. It is activated by the M4 mode bit and
must be turned off in full page mode.
The active part of the line is protected against
parasitic sync insertion. The modified sync is active
on all output pins (ie CSYNC if C7 is set, VIDEO
OUT1, VIDEO OUT2).
A jitter greater than 0.42usec cannot be cancelled.
3.3 - Full Page Mode Behavior
In this case, the PLL is locked on an internal 64usec
reference derived from the 4*fsc quartz.
The STV5730A generates a non interlace output.
4 - MUTE
The STV5730A monitors the sync to determine
whether it is a stable signal or not.
MUTE = high : no stable signal
MUTE = low : stable CVBS input signal
The MUTE search time constant may be either
8 lines or 32 lines, according to the M3 mode bit.
The signal that is delivered to the MUTE output pin
is synchronized on the vertical sync if M11 is
cleared. It is forced low if the M2 mode bit is low.
This signal may be monitored by the microproces-
sor to switch the STV5730A from mixed mode to
full page mode and vice versa (using the C0 control
bit).
5 - THE LUMA GENERATOR
The luma signal is generated by the STV5730A
from timing information created by the character
and video timing generators and voltage levels
created by the internal bias level generator or
entered on the LESCREEN and LECHAR pins (as
selected by the C10 control bit).
The luma signal is output on the YOUT pin to allow
the user to notch filter it. It is then re-input on the
YIN pin. YOUT and YIN may be connected together
for minimal cost applications.
STV5730A
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