IRF740STRLPBF Vishay, IRF740STRLPBF Datasheet - Page 7

MOSFET N-CH 400V 10A D2PAK

IRF740STRLPBF

Manufacturer Part Number
IRF740STRLPBF
Description
MOSFET N-CH 400V 10A D2PAK
Manufacturer
Vishay
Type
Power MOSFETr
Datasheets

Specifications of IRF740STRLPBF

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Standard
Rds On (max) @ Id, Vgs
550 mOhm @ 6A, 10V
Drain To Source Voltage (vdss)
400V
Current - Continuous Drain (id) @ 25° C
10A
Vgs(th) (max) @ Id
4V @ 250µA
Gate Charge (qg) @ Vgs
63nC @ 10V
Input Capacitance (ciss) @ Vds
1400pF @ 25V
Power - Max
3.1W
Mounting Type
Surface Mount
Package / Case
D²Pak, TO-263 (2 leads + tab)
Transistor Polarity
N Channel
Continuous Drain Current Id
10A
Drain Source Voltage Vds
400V
On Resistance Rds(on)
550mohm
Rds(on) Test Voltage Vgs
10V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Configuration
Single
Resistance Drain-source Rds (on)
0.55 Ohms
Drain-source Breakdown Voltage
400 V
Gate-source Breakdown Voltage
+/- 20 V
Continuous Drain Current
10 A
Power Dissipation
3.1 W
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Number Of Elements
1
Polarity
N
Channel Mode
Enhancement
Drain-source On-res
0.55Ohm
Drain-source On-volt
400V
Gate-source Voltage (max)
±20V
Operating Temp Range
-55C to 150C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
2 +Tab
Package Type
D2PAK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91055.
Document Number: 91055
S11-1049-Rev. C, 30-May-11
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
Re-applied
voltage
Reverse
recovery
current
+
R
-
g
D.U.T.
Note
a. V
Driver gate drive
D.U.T. l
D.U.T. V
Inductor current
GS
This document is subject to change without notice.
= 5 V for logic level devices
P.W.
SD
DS
waveform
waveform
Peak Diode Recovery dV/dt Test Circuit
Fig. 14 - For N-Channel
Ripple ≤ 5 %
Body diode forward drop
Period
Body diode forward
+
-
• dV/dt controlled by R
• Driver same type as D.U.T.
• I
• D.U.T. - device under test
Diode recovery
SD
current
controlled by duty factor “D”
Circuit layout considerations
dV/dt
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
dI/dt
D =
-
g
Period
P.W.
+
V
I
V
SD
GS
IRF740S, SiHF740S
DD
= 10 V
+
-
V
DD
a
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Vishay Siliconix
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7

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