821054PQF Integrated Device Technology (Idt), 821054PQF Datasheet - Page 11

• Manufacturer Part Number: 821054PQF
• Description: Audio Codec 4ADC / 4DAC 64-Pin PQFP
• Manufacturer: Integrated Device Technology (Idt)
• Type: PCMr

Specifications of 821054PQF

• Package: 64PQFP
• Number Of Channels: 4ADC /4 DAC
• Number Of Dacs: 4
• Operating Supply Voltage: 5 V

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
2.2
2.2.1
users to optimize the performance of the IDT821054 for the system.
Figure - 4
programmable blocks.
2.2.2
separately in the IDT821054.
can be selected as 0 dB or 6 dB. The selection is done by the GAD bit in
LREG9. It is 0 dB by default.
can be selected as 0 dB or -6 dB. The selection is done by the GDA bit
in LREG9. It is 0 dB by default.
(GTX) is programmable from -3 dB to +12 dB with minimum 0.1 dB step.
If the CS[5] bit in local register LREG1 is ‘0’, the GTX filter is disabled. If
the CS[5] bit is ‘1’, the GTX is programmed by the coefficient RAM.
Several blocks are programmable for signal processing. This allows
The programmable digital filters are used to adjust gain and
Abbreviation List:
LPF/AA: Anti-Alias Low-pass Filter
LPF/SC: Smoothing Low-pass Filter
LPF: Low-pass Filter
HPF: High-pass Filter
GIS: Gain for Impedance Scaling
D1: 1st Down Sample Stage
D2: 2nd Down Sample Stage
U1: 1st Up Sample Stage
U2: 2nd Up Sample Stage
UF: Up Sampling Filter (64 k - 128 k)
The analog gain and digital gain of each channel can be adjusted
For each individual channel, the analog A/D gain in the transmit path
For each individual channel, the analog D/A gain in the receive path
For each individual channel, the digital gain in the transmit path
For each individual channel, the digital gain in the receive path
VOUT
VIN
DSP PROGRAMMING
SIGNAL PROCESSING
GAIN ADJUSTMENT
shows the signal flow for each channel and indicates the
Analog
LPF/AA
LPF/SC
LREG1: CS[2]
CS[2] = 1: enable (normal)
CS[2] = 0: disable (cut)
∑
−
∆
@2 MHz
∑
−
∆
GIS
LREG1: CS[0]
CS[0] = 1: enable (normal)
CS[0] = 0: disable (cut)
U1
D1
UF
Figure - 4 Signal Flow for Each Channel
@64 KHz
IMF
Transmit Path
Receive Path
ECF
LREG1: CS[1]
CS[1] = 1: enable (normal)
CS[1] = 0: disable (cut)
GRX
GTX
11
impedance, balance transhybrid and correct frequency response. All the
coefficients of the digital filters can be calculated automatically by a
software provided by IDT. When users provide accurate SLIC model,
impedance and gain requirements, this software will calculate all the
coefficients automatically. After loading these coefficients to the
coefficient RAM of the IDT821054, the final AC characteristics of the line
card (consists of SLIC and CODEC) will meet the ITU-T specifications.
(GRX) is programmable from -12 dB to +3 dB with minimum 0.1 dB step.
If the CS[7] bit in LREG1 is ‘0’, the GRX filter is disabled. If the CS[7] bit
is ‘1’, the GRX is programmed by the coefficient RAM.
2.2.3
VOUT for each channel. This feedback synthesizes the two-wire
impedance of the SLIC. The programmable Impedance Matching Filter
(IMF) and Gain of Impedance Scaling filter (GIS) work together to realize
impedance matching. If the CS[0] bit in LREG1 is ‘0’, the IMF is
disabled. If the CS[0] bit is ‘1’, the IMF coefficient is programmed by the
coefficient RAM. If the CS[2] bit in LREG1 is ‘0’, the GIS filter is disabled.
If the CS[2] bit is ‘1’, the GIS coefficient is programmed by the coefficient
RAM.
U2
D2
IMF: Impedance Matching Filter
ECF: Echo Cancellation Filter
GTX: Gain for Transmit Path
GRX: Gain for Receive Path
FRX: Frequency Response Correction for Transmit
FRR: Frequency Response Correction for Receive
CMP: Compression
EXP: Expansion
TSA: Time Slot Assignment
The IDT821054 provides a programmable feedback path from VIN to
@16 KHz
LPF
LPF
IMPEDANCE MATCHING
FRX
FRR
@8 KHz
FSK
LREG1: CS[3]
CS[3] = 1: enable (normal)
CS[3] = 0: disable (bypass)
HPF
INDUSTRIAL TEMPERATURE RANGE
Tone
Dual
Bold Black Framed: Programmable Filters
Fine Black Framed: Fixed Filters
Level Meter
CUT-OFF-PCM
CMP
EXP
TS
TSA
TSA
PCM Highway
DR1/DR2
DX1/DX2