821054PQF Integrated Device Technology (Idt), 821054PQF Datasheet - Page 25

• Manufacturer Part Number: 821054PQF
• Description: Audio Codec 4ADC / 4DAC 64-Pin PQFP
• Manufacturer: Integrated Device Technology (Idt)
• Type: PCMr

Specifications of 821054PQF

• Package: 64PQFP
• Number Of Channels: 4ADC /4 DAC
• Number Of Dacs: 4
• Operating Supply Voltage: 5 V

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
GREG6: MCLK Selection and Channel Program Enable, Read/Write (25H/A5H)
GREG7: A/
CHclk1[3:0] = 1000:
CHclk1[3:0] = 1001:
CHclk1[3:0] = 1010:
CHclk1[3:0] = 1011:
CHclk1[3:0] = 1100:
CHclk1[3:0] = 1101:
CHclk1[3:0] = 1110:
CHclk1[3:0] = 1111:
The higher 4 bits (CE[3:0]) in this register are used to specify the desired channel(s) before addressing local registers or Coe-RAM. The
CE[0] to CE[3] bits indicate the program enable state for Channel 1 to Channel 4 respectively.
CE[0] = 0:
CE[0] = 1:
CE[1] = 0:
CE[1] = 1:
CE[2] = 0:
CE[2] = 1:
CE[3] = 0:
CE[3] = 1:
The lower 4 bits (Sel[3:0]) in this register are used to select the Master Clock frequency.
Sel[3:0] = 0000:
Sel[3:0] = 0001:
Sel[3:0] = 0010:
Sel[3:0] = 0110:
Sel[3:0] = 1110:
Sel[3:0] = 0101:
Sel[3:0] = 1101:
Sel[3:0] = 0100:
Sel[3:0] = 1100:
The A/
A-
A-
The Voice Data Select bit (VDS) defines the format of the voice data:
VDS = 0:
VDS = 1:
The Clock Slope bits (CS[2:0]) select single or double clock and clock edges of transmitting and receiving data.
CS[2] = 0:
CS[2] = 1:
CS[1:0] = 00:
CS[1:0] = 01:
Command
Command
µ
µ
µ
I/O data
I/O data
-law, Linear/Compressed Code, Clock Slope and Delay Time Selection, Read/Write (26H/A6H)
= 0:
= 1:
µ
-law select bit (A-
CE[3]
R/W
R/W
A-µ
b7
b7
µ
chclk1 outputs a digital signal with the frequency of 1000/16 Hz;
chclk1 outputs a digital signal with the frequency of 1000/18 Hz;
chclk1 outputs a digital signal with the frequency of 1000/20 Hz;
chclk1 outputs a digital signal with the frequency of 1000/22 Hz;
chclk1 outputs a digital signal with the frequency of 1000/24 Hz;
chclk1 outputs a digital signal with the frequency of 1000/26 Hz;
chclk1 outputs a digital signal with the frequency of 1000/28 Hz;
the output of chclk1 is set to low permanently.
Disabled, Channel 1 can not receive programming commands (default);
Enabled, Channel 1 can receive programming commands;
Disabled, Channel 2 can not receive programming commands (default);
Enabled, Channel 2 can receive programming commands;
Disabled, Channel 3 can not receive programming commands (default);
Enabled, Channel 3 can receive programming commands;
Disabled, Channel 4 can not receive programming commands (default);
Enabled, Channel 4 can receive programming commands.
8.192 MHz
4.096 MHz
2.048 MHz (default)
1.536 MHz
1.544 MHz
3.072 MHz
3.088 MHz
6.144 MHz
6.176 MHz
A-law is selected (default)
µ
Compressed code (default)
Linear code
Single clock (default)
Double clock
transmits data on rising edges of BCLK, receives data on falling edges of BCLK (default).
transmits data on rising edges of BCLK, receives data on rising edges of BCLK.
) selects the companding law:
-law is selected.
CE[2]
VDS
b6
b6
0
0
CE[1]
CS[2]
b5
b5
1
1
CE[0]
CS[1]
25
b4
b4
0
0
Sel[3]
CS[0]
b3
b3
0
0
Sel[2]
OC[2]
b2
b2
1
1
INDUSTRIAL TEMPERATURE RANGE
Sel[1]
OC[1]
b1
b1
0
1
Sel[0]
OC[0]
b0
b0
1
0