MT8952BP1 Zarlink, MT8952BP1 Datasheet - Page 14

• Manufacturer Part Number: MT8952BP1
• Description: PB FREE HDLC CONTROLLER, PLCC
• Manufacturer: Zarlink

MT8952B
A typical connection to the HDLC Protocol Controller
is shown in Figure 14. The parallel port interfaces
with 6800/6809 type processors. The bits A0-A3 are
the addresses of various registers in the Protocol
Controller. The microprocessor can read and write
to these registers treating them as memory
locations.
The serial port transmits/receives the packetized
data. It can be connected to a digital transmission
medium or to a digital network interface circuit. The
TEOP and REOP are the ‘end of packet’ signals on
transmit and receive direction respectively. F0i
and CKi are the timing signals with CKi accepting
either the bit rate clock or 2 x bit rate clock in the
internal timing mode. TxCEN and RxCEN are the
enable inputs in the External Timing Mode.
WD is the output of the watchdog timer. It goes LOW
when the timer times out or if the RST input is held
LOW. This output can be used to reset the
associated microprocessor. The RST is
LOW input which resets the entire circuitry.
Applications
The MT8952B has a number of applications for
transferring data or control information over a digital
channel while providing built-in error detection
capability.
Digital Network Interface Circuit), it can be used to
transmit digital data over a twisted wire pair.
The block schematic of one such application is
shown in Figures 15 and 16.
3-74
PROCESSORS
INTERFACING
PARALLEL
WITH 6809
TYPE
In combination with the MT8972 (the
ISO-CMOS
They refer to the
D0-D7
A0-A3
R/W
Figure 14 - Typical Connection Diagram
IRQ
WD
CS
E
an active
TIMING AND CONTROL
F0i
HDLC Protocol
V
MT8952B
DD
Controller
CKi
V
primary and secondary ends of a voice/data
communication link using the Digital Network
Interface Circuits (DNIC). Each end is associated
with one DNIC which interfaces twisted wire pair to
the digital data rate up to 160kbps (2B+D, framing
signal and housekeeping information).
Primary End of the Link:
The MT8952B is operating in the internal timing
mode with the C-channel transceiver action enabled.
The processor loads the data or control information
(D Channel) in the transmit FIFO which is packetized
in HDLC format and shifted out serially during the
selected channels of the outgoing ST-BUS (CDSTo).
The channels and the number of bits per frame
(frame period=125µsec) can be selected by TC0-
TC3 bits in the Timing Control Register.
channel 1 is reserved for the C-channel information
and channels 2 and 3 carry B-channels (64 kbps
each), the D-channel information can only be sent on
channel-0. Similarly the incoming packets on CDSTi
are loaded into receive FIFO after the removal of all
overhead bits and checked for any errors.
microprocessor will then read the data from the
receive FIFO.
The DNIC (MT8972) is selected to operate in single
port, master mode with the digital network (DN)
option enabled. The B-channels, B1 and B2, are
shown connected directly to the DNIC. Hence, these
should be in ST-BUS format enabled at the
appropriate timeslot (channels 2 and 3). It can be
the outputs of voice codecs (MT896X) providing
voice communication or data codecs (MT8950) for
SS
RST
CDSTo
TEOP
TxCEN
CDSTi
REOP
RxCEN
SERIAL PORT
FORMATTED
WITH
DATA
Since
The