MT8952BP1 Zarlink, MT8952BP1 Datasheet - Page 18

• Manufacturer Part Number: MT8952BP1
• Description: PB FREE HDLC CONTROLLER, PLCC
• Manufacturer: Zarlink

MT8952B
AC Electrical Characteristics
Voltages are with respect to ground (V
† Timing is over recommended temperature & power supply voltages (V
‡ Typical figures are at 25
3-78
10
11
12
1
2
3
4
5
6
7
8
9
NOTE: The write cycle can be initiated either by the falling edge of CS or the rising edge of E clock whichever occurs last. Similarly
the cycle can be terminated by CS (rising edge) or E clock (falling edge) whichever occurs first. The timing relations are to be
referenced from the active edge initiating or terminating the cycle
Delay between CS and E clock
Cycle time
E Clock pulse width HIGH
E Clock pulse width LOW
Read/Write setup time
Read/Write hold time
Address setup time
Address hold time
Data setup time (write)
Data hold time (write)
E clock to valid data delay
Data hold time (read)
A0-A3
D0-D7
CS
CS
R/W
E
E
Characteristics
ISO-CMOS
°
C and are for design aid only: not guaranteed and not subject to production testing.
t
CSE
t
t
SS
AS
RWS
) unless otherwise stated.
Figure 17 - Timing Information for MPU Write
t
CSE
†
- Microprocessor Interface -
t
AH
Sym
t
t
t
t
t
t
t
t
t
t
t
t
RWH
DHW
EWH
RWS
DSW
CSE
CYC
EWL
t
DZH
DHZ
t
DZL
DLZ
AS
AH
t
r
t
Min
205
145
EWH
60
20
10
20
60
35
10
10
0
DD
Typ
=5V
t
t
f
DSW
‡
±
5%, V
Max
145
60
SS
t
=0V, T
RWH
t
DHW
(Figures 17 and 18)
Units
A
=–40 to 85
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYC
t
EWL
Test load circuit 1 (Fig. 26)
C
Test load circuit 3 (Fig. 26)
E clock initiates and
terminates the write cycle
CS initiates and
terminates the write cycle
°
L
C).
=200pF
Test Conditions