SI2493-C-FT Silicon Laboratories Inc, SI2493-C-FT Datasheet - Page 102

• Manufacturer Part Number: SI2493-C-FT
• Description: 56 KBPS, V.92 ISOMODEM SYSTEM-SIDE - LEAD-FREE TSSOP 0 TO 7
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-C-FT

• Mfg Application Notes: SI2493/57/34/15/04, Appl Note AN93
• Data Format: V.21, V.22, V.23, V.29, V.32, V.34, V.90, V.92, Bell 103, Bell 212A
• Baud Rates: 56k
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN93
The parallel interface uses the FIFOs to buffer data in
the same way as serial mode. The main difference is
the additional control pins, RD, WR, CS, and the
addition of Parallel Interface Register 0 and Parallel
Interface Register 1. Flow control must be implemented
by monitoring TXE and RXF in Parallel Register 1.
There is no protection against FIFO overflow. Data
transmitted when the TX FIFO is full is lost.
The register, Parallel Interface register 0 or 1, available
to the Si2493/57/34/15/04 data pins, depends upon the
state of address pin A0. When A0 is low (logic 0), the
data pins D7–D0 and the parallel mode control pins
provide an interface to the transmit and receive FIFOs
through Parallel Interface Register 0. The functions of
D7–0 when A0 = 0
high (logic 1), the data pins, D7–D0, and the parallel
mode control pins provide an interface to the signals in
Parallel Interface Register 1. The functions of D7–D0
when A0 = 1
data rate is approximately 350 kbps (45 kBps).
3.4.5. Parallel Interface Register 0
This register receives transmit data from the parallel
port and provides received data to the parallel port. In
parallel mode, eight data bits are loaded into the TX
FIFO for every parallel write to Register 0. Transmit and
receive flow control in the parallel mode is controlled by
102
Table 72. Parallel Interface Register 0 Bit Map
Pin
10
11
15
16
17
22
23
3
8
9
7:0
Table 71. Pin Function Changes in Parallel
Bit
TX/RX[7:0]
Serial Mode
b
Function
CLKOUT
Name
are listed in Table 73. The maximum burst
AOUT
RXD
ESC
DCD
RTS
TXD
CTS
INT
RI
b
Interface Mode
are listed in Table 72. When A0 is
Function
Transmit/Receive Data
Parallel Mode
Function
WR
INT
RD
CS
D7
D0
D1
D3
D4
A0
Rev. 0.9
the RTS and CTS bits and the RXF and TXE bits in
Parallel Register 1. The operation of RTS and CTS is
analogous to that in Serial mode. These bits control the
transfer of data to and from a 1024 byte software buffer.
Flow control with TXE prevents block writes from
overflowing the TX hardware FIFO. All bits in this
register are read/write. The register resets to 0x63 after
a manual or power-on reset.
3.4.6. Parallel Interface Register 1
This register controls the flow of data in the parallel
mode and is reset to 0x63.
Bit 7 (RXF) is a read/write bit that gives the status of the
12-byte deep receive FIFO. If RXF = 0
FIFO contains less than 10 bytes. If RXF = 1
receive FIFO contains more than 9 bytes and is full or
almost full. Writing RXF = 0
Bit 6 (TXE) is a read/write bit that gives the status of the
14-byte deep transmit FIFO. If TXE = 0
FIFO contains three or more bytes. If TXE = 1
transmit FIFO contains two or fewer bytes. Writing
TXE = 0
state of TXE.
Bit 5 (REM) is a read-only bit that indicates when the
receive FIFO is empty. If REM = 0
contains valid data. If REM = 1
empty. The timer interrupt set by U6F ensures that RX
FIFO contents ≤ 9 bytes are serviced properly.
Bit 4 (INTM) is a read/write bit that controls whether or
not INT (bit 3) triggers the INT pin (Si2493/57/34/15/04,
pin 15 in the parallel mode).
Bit 3 (INT) is a read-only bit that reports Interrupt status
in the parallel mode. If INT = 0
occurred. If INT = 1
PPD, RI, or DCD (U70 bits 4, 3, 2, 1, 0, respectively)
has occurred. This bit is reset by :I.
Data Bit
D7
D6
D5
D4
D3
D2
D1
D0
Table 73. Parallel Register 1 Signals
b
clears the interrupt but does not change the
Signal
INTM
REM
RXF
ESC
CTS
TXE
RTS
INT
b
, an interrupt due to CID, OCD,
b
Receive FIFO Almost Full
Transmit FIFO Almost Full
Receive FIFO Empty
Interrupt Mask
Interrupt
Escape
Request-to-Send
Clear-to-Send
clears the interrupt.
b
, the receive FIFO is
b
b
, no interrupt has
, the receive FIFO
Function
b
b
, the transmit
, the receive
b
b
, the
, the