PM7543FSZ Analog Devices Inc, PM7543FSZ Datasheet - Page 8

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PM7543FSZ

Manufacturer Part Number
PM7543FSZ
Description
DAC 1-CH R-2R 12-Bit 16-Pin SOIC
Manufacturer
Analog Devices Inc
Datasheets

Specifications of PM7543FSZ

Package
16SOIC
Resolution
12 Bit
Architecture
R-2R
Digital Interface Type
Serial
Number Of Outputs Per Chip
1
Output Type
Current
Full Scale Error
±2 LSB
Integral Nonlinearity Error
±1 LSB
Settling Time
1µs
Number Of Bits
12
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power Dissipation (max)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PM7543FSZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
I
FIGURE 3: PM-7543 Equivalent Circuit (All Inputs LOW)
PM-7543
and to lOUT' when aU bits are HIGH. The ILEAKAGE c urrent
the substrate. The 1/4096 current source represents
tor.
FIGURE 4: PM- 7543 Equivalent Circuit (All Digital Inputs HIGH)
EQUIVALENT CIRCUITANALVSIS
Figures 3 and 4 show equivalent circuits for the PM-7543's inter-
nal DAC with all bits LOW and HIGH, respectively. The refer-
ence current is switched to IOUT2 when all data bits are LOW,
source
stant 1-bit current drain through the ladder's terminating resis-
Output capacitance is dependent upon the digital
This is because
creases with applied gate voltage. This output capacitance var-
ies between the low and high values.
DYNAMIC PERFORMANCE
OUTPUT IMPEDANCE
The output resistance, as in the case of the output capacitance,
varies with the digital input code. This resistance,
into the 'OUT1terminal, may be between 11kn (the feedback
resistor alone when all digital inputs are LOW) and 7.5kQ (the
feedback resistor in parallel with approximately 30kQ of the R-
2R ladder network resistance when any single bit logic is HIGH).
these variations.
Static accuracy and dynamic performance will be affected by
v""
VREF
'R"
'""
- R. , 0kH
- R-\Ok"
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is the
t
t
combination of surface and junction leakages to
the gate capacitance
t
t
of MOS transistors
R" 10'H
-
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Page
looking back
input
FI,..OBACK
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AFEEDSACk
'OUT 1
'OUT>
21
the con-
code.
in-
-8-
The gain and phase stability of the output amplifier, board lay-
capacitor may be required when high-speed operational ampli-
fiers are used. It may be connected across the amplifiers feed-
critically damp the output.
2. Power supply decoupling at the device socket and use of
out, and power supply decoupling will all affect the dynamic
performance of the PM-7543. The use of a small compensation
back resistor to provide the necessary
The considerations
APPLICATIONS INFORMATION
APPLICATION
1. Phase compensation
In most applications, linearity depends upon
IOUT1' ' OUT2' a nd AGND (pins 1,2, and 3) being exactly equal to
each other. In most applications, t he DACis
external
bias current and low drift over temperature. The amplifier's input
offset voltage should be nulled to less than :t200~V (less than
The operational amplifier's non inverting input should have a
Figures 7 and 8). The amplifier selected should have a low input
minimum resistance connection to ground; the usual bias cur-
rent compensation
cause a variable offset voltage
error. Allgrounded pins should
point, avoiding ground loops. The VOD power supply should
system.
transition
graph under the Typical
supply current decreases
supply rails (Voo or DGND), i.e. rapidly slewing logic signals that
settle very near the supply rails will minimize supply current.
OUTPUT
When using high speed op amps, a small feedback capacitor
AC
10% of 1 LSB).
have a low noise level with no transients
It is recommended that the digital inputs be taken
V DOvia a
mulation of static charge if the PC card is disconnected
Peak supply current flows as the
(typically 5-30pF) should be used across the amplifier to mini-
mize overshoot
speed applications,
gain/phase
that
compensation
lected for the desired performance. It has already been noted
minal. This
should have a bias current which is low over the temperature
range of interest.
proper grounding techniques.
specifications
an offset can be caused
op amp with its
region
AMPLIFIER
high
margin specifications
resistor should not be used. Instead, the amplifier
value (1 Mn) resistor; this will prevent the
resistor in the amplifier's
TIPS
and ringing, For low speed or static applications,
(see the Supply
of the amp1ifier are not very critical. In
resistor
when using high-speed amplifiers are:
slew rate, settling time, open-loop
CONSIDERATIONS
(see Figures 7 and 8).
noninverting
as the input
should not be used. This
Performance
by including the
tie to a single common ground
appearing as a varying output
Current
digital inputs
of the amplifier
input tied to ground (see
phase compensation
voltage approaches
non inverting input
vs
greater than + 17V.
Characteristics).
logic
usual bias current
connected to an
pass through the
the
should be se-
Input Voltage
to ground or
potential of
resistor can
gain, and
from the
REV. 0
accu-
high-
The
ter-
the
to

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