PM7543FSZ Analog Devices Inc, PM7543FSZ Datasheet - Page 9

• Manufacturer Part Number: PM7543FSZ
• Description: DAC 1-CH R-2R 12-Bit 16-Pin SOIC
• Manufacturer: Analog Devices Inc

Specifications of PM7543FSZ

• Package: 16SOIC
• Resolution: 12 Bit
• Architecture: R-2R
• Digital Interface Type: Serial
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: ±2 LSB
• Integral Nonlinearity Error: ±1 LSB
• Settling Time: 1µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ANALOG DEVICES fAX-ON-DEMAND HOTLINE
FIGURE5: Simplified Circuit
Static accuracy is affected by the variation in the DAC's output
resistance. This variation is best illustrated by using the circuit
of Figure 5 and the equation:
where Ro is a function of the digital code, and:
Therefore, the offset gain varies as follows:
VERROR,
The error difference is 2/3 Vos'
Since one LSB has a weight (for VREF= +1OV)of 2.4mV for the PM-
7543. itis clearly important that Vas be minimized, either using the
amplifier's nullingpins, an external nullingnetwork, or by selection of
REV. 0
VERROR
VERR0R2
FIGURE 6: Timing Diagram
at code 0011 1111 1111,
Ao = 1Oka for more than four bits of logic 1,
at code 0100 0000 0000,
Ro = 30kn for any single bit of logic 1.
v~~-~-
=
=
=
fA r
Vas
Vas (1
Voo 1 + ---
If'
(
(
1 +!Qk!~
+
(STB1ST
30kn
10ka
1okQ
r;:~)
'STRO
2R
i:P1 AND LD2
.
R
,
BEIHPUT
)
)
,
H'. "I
2, STB4)
=
=
4/3 Voo
2 Vas
SRI
2R
=i~~
NOTES;
"DATA LOADED ,,"SB FIRST.
os>< o s< -
'STROBE
A
STB3IS USED TO STROBE SERIAL DATA
BITS INTO REGISTER.
-
WAVEFORM IS IItVERTED IF
Page 22
HC
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1'1"1
1-
r
_.~'
BIT1
tn.,
t'Tltt.m
1ST.'
1ST.'
trnli
tin;
lfio;
X
- -
I
....
'
10"" to
f2
'0
..3. 0..0
X=:
-9-
I
The microprocessor
chip or with the use of external decoding circuitry (see Fig-
ure 11).
STB2, or STB4. The strobe inputs are active on the rising edge.
~t
an amplifier with inherently fow Vos' Amplifiers with sufficiently
low Vos include PMl's OP- 77, OP-97. OP-O7, OP-27 and OP-42-
signed with multiple STROBE and LOAD inputs to maximize
interfacing options, Control signals decoding may be done on-
Serial data can be clocked into the input register with STB 1.
STB3 may be used with a falling edge to clock-in data.
Holding any STROBE input at its selected state (i.e. STB1.
STB2or STB4at logicHIGHor
When a new data word has
ter to
STB1 (Pin 4), STB2 (Pin
data into
CLR
When LOW, 12-bit DAC register is forced to a zero code
0000 0000)
INTERFACE LOGIC OPERATION
prevent any further
it is transferred
inputs.
The CLA input allows asynchronous
input
the
to -V REF'
INTERFACE INPUT DESCRIPTION
Strobe. Inputs Active on Rising Edge. Selected to load serial
STB3
ing Edge. Selected to load serial
Table 1 for details.
LD1 (Pin 5), LD2 (Pin 9)
Low. Selected together
DAC register.
:X
INTOINPUTREGISTER
LOADSERIALDATA
analog
0000 0000
registers.
(Pin 13)
(Pin
input register. See Table 1 for details.
BIT 11
output going to OV.ln bipolar mode,
10) -Input Register Strobe Input. Active on Fail-
regardless of other interface inputs,
-
..
While
0000. Th is reset does not affect data held in the
to the DAC register by asserting both LOAD
X
Clear Input. Active Low. Asynchronous.
data input.
4
interface of the PM-7543 has been de-
8~~~2
in unipolar
DATA INTOCAe
t... +--1
LOAD INPUT REGISTER'S
to load contents of Input Register into
-
8),
Load DAC Register
been entered
x=
':'0' r
l::J
STB4 (Pin 11)
S"f'B3
mode, a CLEAR will result in
REGISTER
data into input register See
resetting of the DAC regis-
at logic
into the input register,
PM-7543
-
the output will go
LOW) will act to
Input Register
Inputs. Active
(0000
l