ADSP-21061LKBZ-160 Analog Devices Inc, ADSP-21061LKBZ-160 Datasheet - Page 20

• Manufacturer Part Number: ADSP-21061LKBZ-160
• Description: DSP Floating-Point 32-Bit 40MHz 40MIPS 225-Pin BGA
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKBZ-160

• Package: 225BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 40 MHz
• Ram Size: 128 KB
• Device Million Instructions Per Second: 40 MIPS
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21061/ADSP-21061L
EXTERNAL POWER DISSIPATION (3.3 V)
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
P
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
and is calculated by:
Table 5. External Power Calculations
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
Note that the conditions causing a worst-case P
from those causing a worst-case P
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Pin Type
Address
MS0
WR
Data
ADDRCLK
P
INT
TOTAL
EXT
—the number of output pins that switch during each cycle
—the maximum frequency at which they can switch (f)
—their load capacitance (C)
—their voltage swing (V
(O)
= 0.074 W
= I
= P
DDIN
EXT
PEXT = O
×
+ (I
V
DD
DDIN2
×
C
× 5.0 V)
×
DD
V
)
No. of Pins
15
1
1
32
1
DD
2
INT
×
f
. Maximum P
50
—
% Switching
50
0
—
EXT
INT
are different
Rev. C | Page 20 of 56 | July 2007
cannot
× C
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
drive high and low at a maximum rate of 1/(2t
strobe can switch every cycle at a frequency of 1/t
switch at 1/(2t
Example: Estimate P
The P
drive:
• A system with one bank of external data memory RAM
• Four 128k × 8 RAM chips are used, each with a load of
• External data memory writes occur every other cycle, a rate
• The instruction cycle rate is 40 MHz (t
(32-bit)
10 pF
of 1/(4t
EXT
equation is calculated for each class of pins that can
× f
× 10 MHz
× 10 MHz
× 20 MHz
× 10 MHz
× 20 MHz
CK
), with 50% of the pins switching
CK
), but selects can switch on each cycle.
EXT
with the following assumptions:
× V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
DD
2
CK
= P
= 0.037 W
= 0.000 W
= 0.010 W
= 0.026 W
= 0.001 W
= 25 ns)
CK
EXT
). The write
CK
. Select pins