ADSP-21061LKBZ-160 Analog Devices Inc, ADSP-21061LKBZ-160 Datasheet - Page 21

• Manufacturer Part Number: ADSP-21061LKBZ-160
• Description: DSP Floating-Point 32-Bit 40MHz 40MIPS 225-Pin BGA
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKBZ-160

• Package: 225BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 40 MHz
• Ram Size: 128 KB
• Device Million Instructions Per Second: 40 MIPS
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
ESD CAUTION
PACKAGE MARKING INFORMATION
The information presented in
the package branding for the ADSP-21061 processor. For a
complete listing of product availability, see
Page
Table 6. Package Brand Information
Parameter
Supply Voltage (V
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Lead Temperature (5 seconds)
Junction Temperature Under Bias
Brand Key
t
pp
Z
ccc
vvvvvv.x
n.n
yyww
Figure 8. Typical Package Marking (Actual Marking Format May Vary)
53.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
DD
)
yyww country_of_origin
S
a
Field Description
Temperature Range
Package Type
Lead Free Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
ADSP-21061
vvvvvv.x n.n
Figure 8
tppZccc
provides details about
Ordering Guide on
Rev. C | Page 21 of 56 | July 2007
than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TIMING SPECIFICATIONS
The timing specifications shown are based on a CLKIN fre-
quency of 40 MHz (t
calculation of timing specifications within the min to max range
of the t
between the derated CLKIN period (t
25 ns:
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, you
cannot meaningfully add parameters to derive longer times.
For voltage reference levels, see
Conditions.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices. (O/D) = Open Drain,
(A/D) = Active Drive.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
5 V
–0.3 V to +7.0 V
–0.5 V to V
–0.5 V to V
200 pF
–65°C to +150°C
280°C
130°C
CK
specification (see
DD
DD
+0.5 V
+0.5 V
DT = t
CK
ADSP-21061/ADSP-21061L
= 25 ns). The DT derating enables the
CK
Table
– 25 ns
Figure 29
3.3 V
–0.3 V to +4.6 V
–0.5 V to V
–0.5 V to V
200 pF
–65°C to +150°C
280°C
130°C
7). DT is the difference
CK
) and a CLKIN period of
under Test
DD
DD
+0.5 V
+0.5 V