ATF-551M4-BLK Avago Technologies US Inc., ATF-551M4-BLK Datasheet - Page 19

• Manufacturer Part Number: ATF-551M4-BLK
• Description: IC PHEMT 2GHZ 2.7V 10MA MINIPAK
• Manufacturer: Avago Technologies US Inc.

Specifications of ATF-551M4-BLK

• Package / Case: 4-MiniPak (1412)
• Mfg Application Notes: ATF-541M4 AppNote
• Transistor Type: pHEMT FET
• Frequency: 2GHz
• Gain: 17.5dB
• Voltage - Rated: 5V
• Current Rating: 100mA
• Noise Figure: 0.5dB
• Current - Test: 10mA
• Voltage - Test: 2.7V
• Power - Output: 14.6dBm
• Configuration: Single Dual Source
• Transistor Polarity: N-Channel
• Power Dissipation: 270 mW
• Drain Source Voltage Vds: 5 V
• Gate-source Breakdown Voltage: - 5 V to 1 V
• Continuous Drain Current: 100 mA
• Maximum Operating Temperature: + 150 C
• Maximum Drain Gate Voltage: - 5 V to 1 V
• Minimum Operating Temperature: - 65 C
• Mounting Style: SMD/SMT
• Channel Type: N
• Drain-gate Voltage (max): -5 to 1V
• Operating Temperature (max): 150C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 4
• Continuous Drain Current Id: 100mA
• Power Dissipation Pd: 270mW
• Noise Figure Typ: 0.5dB
• Rf Transistor Case: MiniPak
• No. Of Pins: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ATF-551M4 Applications Information
Introduction
Avago Technologies’s ATF-551M4 is a low noise
enhancement mode PHEMT designed for use in low
cost commercial applications in the VHF through 10
GHz frequency range. As opposed to a typical depletion
mode PHEMT where the gate must be made negative
with respect to the source for proper operation, an
enhancement mode PHEMT requires that the gate
be made more positive than the source for normal
operation. Therefore a negative power supply voltage is
not required for an enhancement mode device. Biasing
an enhancement mode PHEMT is much like biasing the
typical bipolar junction transistor. Instead of a 0.7V base
to emitter voltage, the ATF-551M4 enhancement mode
PHEMT requires a nominal 0.47V potential between the
gate and source for a nominal drain current of 10 mA.
Matching Networks
The techniques for impedance matching an en-
hancement mode device are very similar to those for
matching a depletion mode device. The only difference
is in the method of supplying gate bias. S and Noise
Parameters for various bias conditions are listed in
this data sheet. The circuit shown in Figure 37 shows a
typical LNA circuit normally used for 900 and 1900 MHz
applications. Consult the Avago Technologies web site
for application notes covering specific designs and ap-
plications. High pass impedance matching networks
consisting of L1/C1 and L4/C4 provide the appropri-
ate match for noise figure, gain, S11 and S22. The
high pass structure also provides low frequency gain
reduction which can be beneficial from the standpoint
of improving out-of-band rejection.
Capacitors C2 and C5 provide a low impedance in-band
RF bypass for the matching networks. Resistors R3 and
R4 provide a very important low frequency termination
for the device. The resistive termination improves low
frequency stability. Capacitors C3 and C6 provide the
RF bypass for resistors R3 and R4. Their value should be
chosen carefully as C3 and C6 also provide a termina-
tion for low frequency mixing products. These mixing
products are as a result of two or more in-band signals
mixing and producing third order in-band distor-
tion products. The low frequency or difference mixing
products are terminated by C3 and C6. For best sup-
pression of third order distortion products based on
the CDMA 1.25 MHz signal spacing, C3 and C6 should
be 0.1 uF in value. Smaller values of capacitance will
not suppress the generation of the 1.25 MHz difference
signal and as a result will show up as poorer two tone
IP3 results.
1
INPUT
Figure . Typical ATF-551M4 LNA with Passive Biasing.
Bias Networks
One of the major advantages of the enhancement
mode technology is that it allows the designer to be
able to dc ground the source leads and then merely
apply a positive voltage on the gate to set the desired
amount of quiescent drain current Id.
Whereas a depletion mode PHEMT pulls maximum
drain current when V
PHEMT pulls only a small amount of leakage current
when V
device threshold voltage, will drain current start to flow.
At a V
current I
suggests a minimum and maximum V
desired amount of drain current will be achieved. It is
also important to note that if the gate terminal is left
open circuited, the device will pull some amount of
drain current due to leakage current creating a voltage
differential between the gate and source terminals.
Passive Biasing
Passive biasing of the ATF-551M4 is accomplished by
the use of a voltage divider consisting of R1 and R2. The
voltage for the divider is derived from the drain voltage
which provides a form of voltage feedback through the
use of R3 to help keep drain current constant. In the
case of a typical depletion mode FET, the voltage divider
which is normally connected to a negative voltage
source is connected to the gate through resistor R4.
Additional resistance in the form of R5 (approximately
10KΩ) is added to provide current limiting for the gate
of enhancement mode devices such as the ATF-551M4.
This is especially important when the device is driven to
P1dB or Psat.
Resistor R3 is calculated based on desired V
available power supply voltage.
R3 =
Zo
V
R1
I
ds
ds
DD
R5
R4
gs
C1
d
+ I
of 2.7V and a nominal V
L1
= 0V. Only when V
– V
will be approximately 10 mA. The data sheet
BB
C3
C2
ds
R2
Q1
L2
L3
Vdd
gs
L4
R3
= 0V, an enhancement mode
C5
C6
(1)
C4
gs
is increased above V
Zo
OUTPUT
gs
of 0.47V, the drain
gs
over which the
ds
, I
ds
th
, the
and