74LVC1G17GW-G NXP Semiconductors, 74LVC1G17GW-G Datasheet - Page 8

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74LVC1G17GW-G

Manufacturer Part Number
74LVC1G17GW-G
Description
Schmitt Trigger Buffer 1-CH Non-Inverting CMOS 5-Pin TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC1G17GW-G

Package
5TSSOP
Logic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number Of Outputs Per Chip
1
Input Signal Type
Single-Ended
Maximum Propagation Delay Time @ Maximum Cl
3.2(Typ)@2.7V|3(Typ)@3.3V|2.2(Typ)@5V ns
Tolerant I/os
5 V
Typical Quiescent Current
0.1 uA
Polarity
Non-Inverting
NXP Semiconductors
12. Waveforms
Table 10.
74LVC1G17
Product data sheet
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
Fig 10. The input A to output Y propagation delay times
Fig 11. Test circuit for measuring switching times
CC
Measurement points are given in
V
Test data is given in
Definitions for test circuit:
R
C
R
V
OL
L
L
T
EXT
Measurement points
= Load resistance.
= Load capacitance including jig and probe capacitance.
= Termination resistance should be equal to the output impedance Z
and V
= External voltage for measuring switching times.
OH
are typical output voltage levels that occur with the output load.
Table
11.
Y output
A input
Table
Input
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
G
All information provided in this document is subject to legal disclaimers.
M
GND
10.
V
V
OH
OL
V
V
I
Rev. 7 — 10 November 2010
CC
CC
CC
I
R T
V
M
DUT
V
CC
V
M
t
PHL
V
O
C L
o
of the pulse generator.
V
mna616
EXT
R L
R L
mnb153
t
Output
V
0.5 × V
0.5 × V
1.5 V
1.5 V
0.5 × V
PLH
M
Single Schmitt trigger buffer
CC
CC
CC
74LVC1G17
© NXP B.V. 2010. All rights reserved.
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